SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The SysClk is distributed to the processor and the integrated peripherals after clock gating. The SysClk frequency is based on the frequency of the clock source and the divisor factor. For example, if the PLL is not being used and the device is not in deep-sleep mode, then the OSYSDIV bit field in the RSCLKCFG register is the divisor used to determine the system clock. If the PLL is being used, then PSYSDIV bit field in the RSCLKCFG register must be programmed as well as the values in the PLLFREQ0 and PLLFREQ1 registers. If the device is in deep-sleep mode, then the DSCLKCFG register can be programmed with the divisor bit field DSSYSYDIV to modify the clock source frequency. Table 4-4 lists the different system clock frequency calculations based on the operation mode, clock source, and PLL encoding.
| Clock Mode | USEPLL (RSCLKCFG) | SYSCLK Value | Divisor Factors Used |
|---|---|---|---|
| Run or sleep | 1 | fVCO / (PSYSDIV + 1) | PSYSDIV bit field in RSCLKCFG; MINT, MDIV in PLLFREQ0; Q, N bits in PLLFREQ1 |
| Run or sleep | 0 | fOSCCLK / (OSYSDIV + 1) | OSYSDIV bit field in RSCLKCFG |
| Deep sleep | PLL not enabled in deep-sleep mode | fOSCCLK / (DSSYSDIV + 1) | DSSYSDIV bit field in DSCLKCFG |