SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Four levels of operation are defined for the microcontroller:
For power-savings purposes, the peripheral-specific RCGCx, SCGCx, and DCGCx registers (for example, RCGCWD) control the clock-gating logic for that peripheral or block in the system while the microcontroller is in Run, Sleep, and deep-sleep mode, respectively. These registers are located in the system control register map starting at offsets 0x600, 0x700, and 0x800, respectively.
NOTE
A change in the RCGCx (or SCGCx, DCGCx, PCx, or SRx) registers may not have an immediate effect on the clock in all situations. Poll the Peripheral Ready (PRx) register to determine when a peripheral is ready to be accessed.
NOTE
If a peripheral is configured to be clock-gated during run, sleep, or deep-sleep mode, software should ensure that there are no pending transfers or register accesses before or immediately after entering the clock-gated mode.