15.3.6.1 System Time Module

The System Time module maintains a 64-bit time and is updated using the MOSC clock source as the PTP clock reference. This time is the source for taking snapshots (timestamps) of the Ethernet frames being transmitted or received. Two methods of updating the system time counter are implemented. The counter can be initialized or corrected using the coarse correction method. In this method, the initial value or the offset value is written to the MAC System Time - Seconds Update (EMACTIMSECU) register along with the MAC System Time - Nanoseconds Update (EMACTIMNANOU) register. For initialization the system time counter is written with the value in these registers, while for system time correction, the offset value is added to or subtracted from the system time.

In the fine correction method, the slave clock frequency drift with respect to the master clock is corrected over a period of time instead of in one clock, as in coarse correction. This helps maintain linear time and does not introduce drastic changes (or a large jitter) in the reference time between PTP Sync message intervals. In this method, an accumulator sums up the contents of the EMACTIMADD register (see Figure 15-11). The arithmetic carry that the accumulator generates is used as a pulse to increment the system time counter. The accumulator and the addend are 32-bit registers. Here, the accumulator acts as a high-precision frequency multiplier or divider.

Figure 15-11 System Time Update Using Fine Correction Method

Initially, the Ethernet slave clock (from the MOSC) is adjusted with a compensation value (as described in the previous paragraph) which is written to the Timestamp Addend Register (TSAR) field in the EMACTIMADD register. This value is calculated as:

The System Time Module requires a 20-MHz PTP reference clock frequency to achieve 50-ns accuracy in the fine correction method. An addend must be written to the Ethernet MAC Time Stamp Addend (EMACTIMADD) register, offset 0x718 to achieve timing synchronization. If the MOSC clock source is 25 MHz, the frequency division ratio (FreqDivisionRatio) of the two is calculated as 25 MHz / 20 MHz = 1.25. Hence, the default addend value to be set in the register is 2³² / 1.25 or 0xCCCC.CCD0. If the reference clock drifts lower, to 24 MHz for example, the ratio is 24 / 20, or 1.2 and the value to set in the addend register is 2³² / 1.20, or 0xDFF1.65D2. The software must calculate the drift in frequency based on the Sync messages and update the EMACTIMADD register, at offset 0x718, accordingly.

If the master to slave delay is initially assumed to be the same for consecutive Sync messages, then the following steps can be used to calculate a new TSAR value. The following algorithm calculates the precise mater to slave delay value to allow for re-synchronization with the master using the new value:

1. At time MasterSyncTime_n the master sends the slave clock a Sync message. The slave receives this message when its local clock is SlaveClockTime_n and computes MasterClockTime_n as:
Equation 51. MasterClockTime_n = MasterSyncTime_n + MasterToSlaveDelay_n
2. The master clock count, MasterClockCount_n, for the current Sync cycle is given by:
Equation 52. MasterClockCount_n = MasterClockTime_n – MasterClockTime_n-1

This assumes that the MasterToSlaveDelay is the same for Sync cycles n and n-1.

3. The slave clock count for current Sync cycle, SlaveClockCount_n is given by:
Equation 53. SlaveClockCount_n = SlaveClockTime_n – SlaveClockTime_n-1
4. The difference between the master and slave clock counts for the current Sync cycle, ClockDiffCount_n, is given by:
Equation 54. ClockDiffCount_n = MasterClockCount_n – SlaveClockCount_n
5. The frequency-scaling factor for the slave clock, FreqScaleFactor_n is given by:
Equation 55. FreqScaleFactor_n = (MasterClockCount_n + ClockDiffCount_n) / SlaveClockCount_n
6. The frequency compensation value, FreqCompensationValue, to be written in the TSAR field of the EMACTIMADD register is:
Equation 56. FreqCompensationValue_n = FreqScaleFactor_n × FreqCompensationValue_n-1

In theory, this algorithm achieves lock in one Sync cycle; however, it may take several cycles, because of changing network propagation delays and operating conditions. This algorithm is self-correcting: if for any reason the slave clock is initially set to a value from the master that is incorrect, the algorithm corrects it at the cost of more Sync cycles.