SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
lists the Cortex-M4 Peripheral SysTick, NVIC, MPU, FPU and SCB registers. The offset listed is a hexadecimal increment to the register's address, relative to the Core Peripherals base address of 0xE000E000 (ending address of 0xE000EFFF).
NOTE
Register spaces that are not used are reserved for future or internal use. Software should not modify any reserved memory address.
Table 2-9lists the memory-mapped registers for the SYSTICK. All register offset addresses not listed in Table 2-9 should be considered as reserved locations and the register contents should not be modified.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 0x10 | STCTRL | SysTick Control and Status Register | Section 2.3.1 |
| 0x14 | STRELOAD | SysTick Reload Value Register | Section 2.3.2 |
| 0x18 | STCURRENT | SysTick Current Value Register | Section 2.3.3 |
Complex bit access types are encoded to fit into small table cells. Table 2-10 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| WC | W | Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |