SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
There are many responses to a tamper event including clearing some or all of Hibernate memory and generating a tamper signal to the System Control Module. The descriptions of the possible event responses follows.
The tamper status is indicated by the STATE bit field of the HIB Tamper Status (HIBTPSTAT) register. The register bits are reset to 0x0 on cold POR. When the tamper I/O is enabled/configured, the STATE field shows 0x1. The STATE field is set to 0x2 when a tamper event is detected. The software may reset the trigger source and the STATE field by writing to the TPCLR bit in the HIBTPCTL register.
When a tamper event is detected, an NMI is generated. The NMI handler is responsible for performing any other system responses, including a simulate POR. If the tamper event was an XOSC fail condition, the part switches to the HIB LFIOSC. Once XOSC is stable, the XOSC may be enabled as the clock source once again.
On a tamper event, software has the option to clear all, the upper half, lower half, or none of the Hibernate memory. The feature is controlled through the MEMCLR field of the HIBTPCTL register.
A tamper event will assert a wake event to the MCU if the WAKE bit in the HIBTPCTL register is set.