SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The general purpose timer has the capability of being clocked by either the system clock or an alternate clock source. By setting the ALTCLK bit in the GPTM Clock Configuration (GPTMCC) register, offset 0xFC8, software can selects an alternate clock source as programmed in the Alternate Clock Configuration (ALTCLKCFG) register, offset 0x138 in the System Control Module. The alternate clock source options available are PIOSC, RTCOSC, and LFIOSC. See Section 4 for additional information.
NOTE
When the ALTCLK bit is set in the GPTMCC register to enable using the alternate clock source, the synchronization imposes restrictions on the starting count value (down count), terminal value (up count) and the match value. This restriction applies to all modes of operation. Each event must be spaced by 4 Timer (ALTCLK) clock periods + 2 system clock periods. If some events do not meet this requirement, then it is possible that the timer block may need to be reset for correct functionality to be restored.
Example: ALTCLK = TPIOSC = 62.5 ns (16 MHz trimmed)
Thclk = 1 µs (1 MHz)
4 × 62.5 ns + 2 × 1 µs = 2.25 µs 2.25 µs / 62.5 ns = 36 or 0x23
The minimum values for the periodic or one-shot with a match interrupt enabled are: GPTMTAMATCHR = 0x23 and GPTMTAILR = 0x46