SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
After enabling or resetting the EEPROM module, software must wait until the WORKING bit in the EEDONE register is clear before accessing any EEPROM registers.
NOTE
Software must ensure there are no flash memory writes or erases pending before performing an EEPROM operation. When the FMC register reads as 0x0000.00000 and the WRBUF bit of the FMC2 register is clear, there are no flash memory writes or erases pending.
EEPROM operations must be completed before entering Sleep or Deep-Sleep mode. Ensure the EEPROM operations have completed by checking the EEPROM Done Status (EEDONE) register before issuing a WFI instruction to enter Sleep or Deep-Sleep.
Writes to words within a block are delayed by a variable amount of time. The application can use an interrupt to be notified when the write is done, or alternatively poll for the done status in the EEDONE register. The variability ranges from the write timing of the EEPROM to the erase timing of EEPROM, where the erase timing is less than the write timing of most external EEPROMs.
Depending on the CPU frequency, the application must program the EEPROM Clock High Time (EBCHT), EEPROM Bank Clock Edge (EBCE) and the EEPROM Wait States (EWS) in the Memory Timing Parameter Register 0 for main flash and EEPROM (MEMTIM0) register at System Control Module offset 0x0C0.
| CPU Frequency range (f) in MHz | Time Period Range (t) in ns | EEPROM Bank Clock High Time (EBCHT) | EEPROM Bank Clock Edge (EBCE) | EEPROM Wait States (EWS) |
|---|---|---|---|---|
| 16 | 62.5 | 0x0 | 1 | 0x0 |
| 16 < f ≤ 40 | 62.5 > t ≥ 25 | 0x2 | 0 | 0x1 |
| 40 < f ≤60 | 25 > t ≥ 16.67 | 0x3 | 0 | 0x2 |
| 60< f ≤80 | 16.67 > t ≥ 12.5 | 0x4 | 0 | 0x3 |
| 80 < f ≤100 | 12.5 > t ≥ 10 | 0x5 | 0 | 0x4 |
| 100< f ≤120 | 10 > t ≥ 8.33 | 0x6 | 0 | 0x5 |
NOTE
The associated flash and EEPROM fields in the MEMTIM0 register must be programmed to the same values. For example, the FWS field must be programmed to the same value as the EWS field.