SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The checksum for TCP, UDP, or ICMP is calculated over a complete frame, and then inserted into its corresponding header field. Because of this requirement this function is enabled only when the TX FIFO is configured for the store-and-forward mode (the TSF bit is set in the EMACDMAOPMODE register).
NOTE
The TX FIFO must be deep enough to store a complete frame before the frame is transferred to the MAC when the checksum offload is being used. If space is not available to accept the programmed burst length of data, the TX/RX Controller starts reading to avoid deadlock. When reading starts, the checksum offload fails and the consequently all succeeding frames may be corrupted because of improper recovery. Therefore, checksum insertion must only be enabled in frames that are less than 2048 – ((PBL + 3) × 4) bytes in size, where PBL is the Programmable Burst Length field in the EMACDMABUSMOD register.