SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The DMA controller is used for all Ethernet transmissions. The Ethernet frames are read from memory and transferred to the TX FIFO by the DMA. When the MAC is available, the frame is transferred from the FIFO. When the end-of-frame (EOF) is transferred, the MAC notifies the DMA the status of the transmission.
The TX FIFO has a depth of 2KB. The FIFO fill level has the capability of triggering the DMA to initiate a burst transfer. The DMA also transfers start-of-frame (SOF), end-of-frame (EOF), CRC and pad-insertion information to the TX/RX Controller so that this information can be passed to the MAC when it is ready for transmission from the TX FIFO.
Data can be transmitted to the MAC in threshold mode or store-and-forward mode. If the TTC field is configured in the Ethernet MAC DMA Operation Mode (EMACDMAOPMODE) register at offset 0xC18 and the TSF bit in the same register is 0x0, then the TX Controller is operating in threshold mode. In this mode, the data is transferred to the MAC when the number of bytes in the FIFO crossed the value configured in the TTC bit field or when the end-of-frame is written before the threshold is crossed. In store-and forward mode, the TTC bit field is configured and the TSF bit is set. Data is transferred to the MAC only when one or more of the following conditions are true:
With these conditions, the TX Controller continues store-and-forward mode even if the Ethernet frame length is bigger than the TX FIFO size.
The TX FIFO can be flushed of all contents by setting the FTF bit in the EMACDMAOPMODE register. This bit is self-clearing and initializes the FIFO pointers to the default state. If the FTF bit is set during a frame transfer from the TX Controller to the MAC, then the TX Controller stops further transfer. Early termination of the transfer causes a underflow event and this status is communicated to the DMA.