SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Certain peripherals, such as the general-purpose timer, trigger an interrupt to the µDMA controller when a programmed event occurs. When a trigger event occurs, the µDMA executes a transfer defined by the ARBSIZ bit field in the DMACHCTL register. If only a single transfer is needed for a µDMA trigger, then the ARBSIZ field is set to 0x1.
If the trigger peripheral generates another µDMA request while the prior one is being serviced and that particular channel is the highest priority asserted channel, the second request is processed as soon as the handling of the first is complete. If two additional trigger peripheral µDMA requests are generated before the completion of the first, the third request is lost.