SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The TX/RX Controller consists of a FIFO memory which buffers and regulates the frames between the system memory and the MAC. It also controls the data transferred between clock domains. Both the transmit and receive data paths are 32-bits wide. The TX FIFO and RX FIFO are each 2KB in depth.
At reset, the TX/RX Controller is configured and ready to manage data flow to and from the DMA to the MAC. Note that the DMA and MAC must be initialized by the application out of reset.