| 31-16 |
RESERVED |
R |
0x0 |
|
| 15 |
CTSEN |
R/W |
0x0 |
Enable Clear To Send.
0x0 = CTS hardware flow control is disabled.
0x1 = CTS hardware flow control is enabled. Data is only transmitted when the UnCTS signal is asserted.
|
| 14 |
RTSEN |
R/W |
0x0 |
Enable Request to Send.
0x0 = RTS hardware flow control is disabled.
0x1 = RTS hardware flow control is enabled. Data is only requested (by asserting UnRTS) when the receive FIFO has available entries.
|
| 13-12 |
RESERVED |
R |
0x0 |
|
| 11 |
RTS |
R/W |
0x0 |
Request to Send.
When RTSEN is clear, the status of this bit is reflected on the U1RTS signal.
If RTSEN is set, this bit is ignored on a write and should be ignored on read. |
| 10 |
DTR |
R/W |
0x0 |
Data Terminal Ready.
This bit sets the state of the UnDTR output. |
| 9 |
RXE |
R/W |
0x1 |
UART Receive Enable.
If the UART is disabled in the middle of a receive, it completes the current character before stopping.
To enable reception, the UARTEN bit must also be set.
0x0 = The receive section of the UART is disabled.
0x1 = The receive section of the UART is enabled.
|
| 8 |
TXE |
R/W |
0x1 |
UART Transmit Enable.
If the UART is disabled in the middle of a transmission, it completes the current character before stopping.
To enable transmission, the UARTEN bit must also be set.
0x0 = The transmit section of the UART is disabled.
0x1 = The transmit section of the UART is enabled.
|
| 7 |
LBE |
R/W |
0x0 |
UART Loop Back Enable.
0x0 = Normal operation.
0x1 = The UnTx path is fed through the UnRx path.
|
| 6 |
RESERVED |
R |
0x0 |
|
| 5 |
HSE |
R/W |
0x0 |
High-Speed Enable.
System clock used is also dependent on the baud-rate divisor configuration.The state of this bit has no effect on clock generation in ISO 7816 smart card mode (the SMART bit is set).
0x0 = The UART is clocked using the system clock divided by 16.
0x1 = The UART is clocked using the system clock divided by 8.
|
| 4 |
EOT |
R/W |
0x0 |
End of Transmission.
This bit determines the behavior of the TXRIS bit in the UARTRIS register.
0x0 = The TXRIS bit is set when the transmit FIFO condition specified in UARTIFLS is met.
0x1 = The TXRIS bit is set only after all transmitted data, including stop bits, have cleared the serializer.
|
| 3 |
SMART |
R/W |
0x0 |
ISO 7816 Smart Card Support.
The application must ensure that it sets
8-bit word length (WLEN set to 0x3) and even parity (PEN set to 1, EPS set to 1, SPS set to 0) in UARTLCRH when using ISO 7816 mode.
In this mode, the value of the STP2 bit in UARTLCRH is ignored and the number of stop bits is forced to 2.
Note that the UART does not support automatic retransmission on parity errors.
If a parity error is detected on transmission, all further transmit operations are aborted and software must handle retransmission of the affected byte or message.
0x0 = Normal operation.
0x1 = The UART operates in Smart Card mode.
|
| 2 |
SIRLP |
R/W |
0x0 |
UART SIR Low-Power Mode.
This bit selects the IrDA encoding mode.
Setting this bit uses less power, but might reduce transmission distances.
0x0 = Low-level bits are transmitted as an active High pulse with a width of 3/16th of the bit period.
0x1 = The UART operates in SIR Low-Power mode. Low-level bits are transmitted with a pulse width which is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate.
|
| 1 |
SIREN |
R/W |
0x0 |
UART SIR Enable.
0x0 = Normal operation.
0x1 = The IrDA SIR block is enabled, and the UART will transmit and receive data using SIR protocol.
|
| 0 |
UARTEN |
R/W |
0x0 |
UART Enable.
If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping.
0x0 = The UART is disabled.
0x1 = The UART is enabled.
|