26.5.14 UARTDMACTL Register (Offset = 0x48) [reset = 0x0]
UART DMA Control (UARTDMACTL)
The UARTDMACTL register is the DMA control register.
UARTDMACTL is shown in Figure 26-17 and described in Table 26-17.
Return to Summary Table.
Figure 26-17 UARTDMACTL Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
DMAERR |
TXDMAE |
RXDMAE |
| R-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
|
Table 26-17 UARTDMACTL Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-3 |
RESERVED |
R |
0x0 |
|
| 2 |
DMAERR |
R/W |
0x0 |
DMA on Error
0x0 = µDMA receive requests are unaffected when a receive error occurs.
0x1 = µDMA receive requests are automatically disabled when a receive error occurs.
|
| 1 |
TXDMAE |
R/W |
0x0 |
Transmit DMA Enable
0x0 = µDMA for the transmit FIFO is disabled.
0x1 = µDMA for the transmit FIFO is enabled.
|
| 0 |
RXDMAE |
R/W |
0x0 |
Receive DMA Enable
0x0 = µDMA for the receive FIFO is disabled.
0x1 = µDMA for the receive FIFO is enabled.
|