| 31-9 |
RESERVED |
R |
0x0 |
|
| 8 |
RI |
R |
0x0 |
Ring Indicator
0x0 = The UnRI signal is not asserted.
0x1 = The UnRI signal is asserted.
|
| 7 |
TXFE |
R |
0x1 |
UART Transmit FIFO Empty.
The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register.
0x0 = The transmitter has data to transmit.
0x1 = If the FIFO is disabled (FEN is 0), the transmit holding register is empty.If the FIFO is enabled (FEN is 1), the transmit FIFO is empty.
|
| 6 |
RXFF |
R |
0x0 |
UART Receive FIFO Full.
The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register.
0x0 = The receiver can receive data.
0x1 = If the FIFO is disabled (FEN is 0), the receive holding register is full.If the FIFO is enabled (FEN is 1), the receive FIFO is full.
|
| 5 |
TXFF |
R |
0x0 |
UART Transmit FIFO Full.
The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register.
0x0 = The transmitter is not full.
0x1 = If the FIFO is disabled (FEN is 0), the transmit holding register is full.If the FIFO is enabled (FEN is 1), the transmit FIFO is full.
|
| 4 |
RXFE |
R |
0x1 |
UART Receive FIFO Empty.
The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register.
0x0 = The receiver is not empty.
0x1 = If the FIFO is disabled (FEN is 0), the receive holding register is empty.If the FIFO is enabled (FEN is 1), the receive FIFO is empty.
|
| 3 |
BUSY |
R |
0x0 |
UART Busy.
This bit is set as soon as the transmit FIFO becomes non-empty (regardless of whether UART is enabled).
0x0 = The UART is not busy.
0x1 = The UART is busy transmitting data. This bit remains set until the complete byte, including all stop bits, has been sent from the shift register.
|
| 2 |
DCD |
R |
0x0 |
Data Carrier Detect
0x0 = The UnDCD signal is not asserted.
0x1 = The UnDCD signal is asserted.
|
| 1 |
DSR |
R |
0x0 |
Data Set Ready
0x0 = The UnDSR signal is not asserted.
0x1 = The UnDSR signal is asserted.
|
| 0 |
CTS |
R |
0x0 |
Clear To Send
0x0 = The U1CTS signal is not asserted.
0x1 = The UnCTS signal is asserted.
|