| 31-18 |
RESERVED |
R |
0x0 |
|
| 17 |
DMATXRIS |
R |
0x0 |
Transmit DMA Raw Interrupt Status.
This bit is cleared by writing a 1 to the DMATXIC bit in the UARTICR register.
0x0 = No interrupt
0x1 = The transmit DMA has completed.
|
| 16 |
DMARXRIS |
R |
0x0 |
Receive DMA Raw Interrupt Status.
This bit is cleared by writing a 1 to the DMARXIC bit in the UARTICR register.
0x0 = No interrupt
0x1 = The receive DMA has completed.
|
| 15-13 |
RESERVED |
R |
0x0 |
|
| 12 |
9BITRIS |
R |
0x0 |
9-Bit Mode Raw Interrupt Status.
This bit is cleared by writing a 1 to the 9BITIC bit in the UARTICR register.
0x0 = No interrupt
0x1 = A receive address match has occurred.
|
| 11 |
EOTRIS |
R |
0x0 |
End of Transmission Raw Interrupt Status.
This bit is cleared by writing a 1 to the EOTIC bit in the UARTICR register.
0x0 = No interrupt
0x1 = The last bit of all transmitted data and flags has left the serializer.
|
| 10 |
OERIS |
R |
0x0 |
UART Overrun Error Raw Interrupt Status.
This bit is cleared by writing a 1 to the OEIC bit in the UARTICR register.
0x0 = No interrupt
0x1 = An overrun error has occurred.
|
| 9 |
BERIS |
R |
0x0 |
UART Break Error Raw Interrupt Status.
This bit is cleared by writing a 1 to the BEIC bit in the UARTICR register.
0x0 = No interrupt
0x1 = A break error has occurred.
|
| 8 |
PERIS |
R |
0x0 |
UART Parity Error Raw Interrupt Status This bit is cleared by writing a 1 to the PEIC bit in the UARTICR register.
0x0 = No interrupt
0x1 = A parity error has occurred.
|
| 7 |
FERIS |
R |
0x0 |
UART Framing Error Raw Interrupt Status.
This bit is cleared by writing a 1 to the FEIC bit in the UARTICR register.
0x0 = No interrupt
0x1 = A framing error has occurred.
|
| 6 |
RTRIS |
R |
0x0 |
UART Receive Time-Out Raw Interrupt Status.
This bit is cleared by writing a 1 to the RTIC bit in the UARTICR register.
For receive timeout, the RTIM bit in the UARTIM register must be set to see the RTRIS status.
0x0 = No interrupt
0x1 = A receive time out has occurred.
|
| 5 |
TXRIS |
R |
0x0 |
UART Transmit Raw Interrupt Status.
This bit is cleared by writing a 1 to the TXIC bit in the UARTICR register or by writing data to the transmit FIFO until it becomes greater than the trigger level, if the FIFO is enabled, or by writing a single byte if the FIFO is disabled.
0x0 = No interrupt
0x1 = If the EOT bit in the UARTCTL register is clear, the transmit FIFO level has passed through the condition defined in the UARTIFLS register.If the EOT bit is set, the last bit of all transmitted data and flags has left the serializer.
|
| 4 |
RXRIS |
R |
0x0 |
UART Receive Raw Interrupt Status.
This bit is cleared by writing a 1 to the RXIC bit in the UARTICR register or by reading data from the receive FIFO until it becomes less than the trigger level, if the FIFO is enabled, or by reading a single byte if the FIFO is disabled.
0x0 = No interrupt
0x1 = The receive FIFO level has passed through the condition defined in the UARTIFLS register.
|
| 3 |
DSRRIS |
R |
0x0 |
UART Data Set Ready Modem Raw Interrupt Status.
This bit is cleared by writing a 1 to the DSRIC bit in the UARTICR register.
0x0 = No interrupt
0x1 = Data Set Ready used for software flow control.
|
| 2 |
DCDRIS |
R |
0x0 |
UART Data Carrier Detect Modem Raw Interrupt Status.
This bit is cleared by writing a 1 to the DCDIC bit in the UARTICR register.
0x0 = No interrupt
0x1 = Data Carrier Detect used for software flow control.
|
| 1 |
CTSRIS |
R |
0x0 |
UART Clear to Send Modem Raw Interrupt Status.
This bit is cleared by writing a 1 to the CTSIC bit in the UARTICR register.
0x0 = No interrupt
0x1 = Clear to Send used for software flow control.
|
| 0 |
RIRIS |
R |
0x0 |
UART Ring Indicator Modem Raw Interrupt Status.
This bit is cleared by writing a 1 to the RIIC bit in the UARTICR register.
0x0 = No interrupt
0x1 = Ring Indicator used for software flow control.
|