SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The USB block receives two clocks. The main peripheral is clocked from the system clock (SYSCLK) while the serialization and deserialization circuitry requires a fixed 60 MHz clock source. When using the integrated USB PHY, the 60 MHz clock is constructed by dividing the PLL VCO output by a dedicated programmable divisor. The divisor is controlled by the USBCC register. When using the ULPI interface, the 60-MHz clock is selected either from the internal PLL VCO path or the ULPI signal USB0CLK. If the source is the PLL VCO path, the USB0CLK signal must be an output; otherwise, USB0CLK is an input. To correctly synchronize with the data between the main block and the serialization and deserialization circuitry, the main block requires fSYSCLK of 30 MHz.
| ULPIEN Bit in USBPC Register | CSD Bit in USBCC Register | 60 MHz Clock Source(1) | USB0CLK Direction |
|---|---|---|---|
| 0 | X | VCO PLL (CLKDIV +1) | Not Used |
| 1 | 0 | VCO PLL (CLKDIV +1) | Output |
| 1 | 1 | USBCLK0 | Input |