27.3.6 USB DMA Controller

The USB includes an integrated eight-channel USB DMA controller for efficient loading and unloading of the endpoint FIFOs. Any Tx Endpoints 1 through 7 and Rx Endpoints 1 through 7 can be assigned to DMA channels 0 through 7. An endpoint and its direction can be assigned to a USB DMA channel through the EP field and DIR bit in the USB DMA Control n (USBDMACTLn) register. The DMA can operate in two modes and can handle packet sizes up to 8K. In addition, the DMA controller can be programmed to conduct transfers using burst of four, eight and sixteen or bursts of unspecified length.

The DMA request lines are individually enabled through the DMAEN bit in the appropriate USB Transmit Control and Status Endpoint n High (USBTXCSRHn) register or USB Receive Control and Status Endpoint n High (USBRXCSRHn) register and operate in two request modes, referred to as DMA Request Mode 0 and DMA Request Mode 1.

When operating in DMA Mode 0, the DMA controller can be only programmed to load and unload one packet, so processor intervention is required for each packet transferred over the USB. This mode can be used with any endpoint, whether it uses Control, Bulk, Isochronous, or Interrupt transactions (that is, including Endpoint 0).

When operating in DMA Mode 1, the DMA controller can be programmed to load and unload a complete bulk transfer (which can be many packets). Once set up, the DMA controller loads and unloads all packets of the transfer, interrupting the processor only when the transfer has completed. DMA Mode 1 can only be used with endpoints that use Bulk transactions.

Each channel can be independently programmed for the selected operating mode. The choice of operating mode must be made through the DMAMOD bit in the USBTXCSRHn and the USBRXCSRHn register. For Rx endpoints operating in Request Mode 0, the DMA request line goes high when a data packet is available in the endpoint FIFO and normally goes low at the end of the cycle in which the 8th from last byte starts to be processed (which happens two transfers minus one clock cycle in advance of the transfer containing this byte). The request line also goes low if the CPU clears the RXRDY bit in the USB Receive Control and Status Endpoint n Low (USBRXCSRLn) register. The behavior of the DMA request lines for Rx endpoints in Request Mode 1 is similar except the request line only goes high when the packet received is of the maximum packet size (as set in the USB Maximum Receive Data Endpoint n (USBRXMAXPn) register). If the packet received is of some other size, the DMA request line stays low. Note, however, that if the Request Mode is switched from Request Mode 1 to Request Mode 0, the request line is asserted if there is a packet in the FIFO in order to allow this prereceived packet to be downloaded.

For Tx endpoints operating in either Request Mode 0 or Request Mode 1, the DMA request line goes high when the endpoint FIFO is able to accept a data packet. It normally goes low one clock cycle after the 8th from last of MAXLOAD bytes in the USBTXMAXPn register have been loaded into the FIFO. The request line also goes low if the CPU sets the TXRDY bit of the USB Transmit Control and Status Endpoint n Low (USBTXCSRLn) register.

The mode selected also affects the generation of endpoint interrupts. In DMA Request Mode 0, no interrupt is generated when packets are received but the appropriate Endpoint interrupt is generated to prompt the loading of all packets. In DMA Request Mode 1, the Endpoint interrupt is suppressed except following the receipt of a short packet (that is, one of less than MAXLOAD bytes). Table 27-2 and Table 27-3 summarize the conditions under which TX and RX Endpoint interrupts are generated.

DMA Request Mode 0 can be used equally well for Bulk, Interrupt or Isochronous transfers. If the endpoint is configured for Isochronous transfers, DMA Request Mode 0 should always be selected where DMA is used. DMA Request Mode 1 is valuable where large blocks of data are transferred to a Bulk endpoint. The USB protocol requires such packets to be split into a series of packets of the maximum packet size for the endpoint (512 bytes for high speed, 64 bytes for full speed).

DMA Request Mode 1 can be used to avoid the overhead of having to interrupt the processor after each individual packet; instead, the processor is only interrupted after the transfer has completed. In some cases, the block of data transferred comprises a predefined number of these packets, that the controlling software counts through the transfer process. In other cases, the last packet in the series may be less than the maximum packet size and the receiver may use this short packet to signal the en16d of the transfer. (If the total size of the transfer is an exact multiple of the maximum packet size, the transmitting software should send a null packet for the receiver to detect.)

Further information on using DMA for Bulk transfers is given in Section 27.3.6.3. DMA transfers may be byte, half-word, or word, as required. However, all the transfers associated with one packet (with the exception of the last) must be of the same width so that the data is consistently byte-, word- or double-word-aligned. The last transfer may contain fewer bytes than the previous transfers in order to complete an odd-byte or odd-word transfer.