27.5.79 USBCC Register (Offset = 0xFC8) [reset = 0x0]
USB Clock Configuration (USBCC)
The USBCC register specifies the clock configuration for the USB controller.
NOTE
When the USB module uses the integrated USB PHY, the MOSC must be the clock source, either with or without using the PLL, and the system clock must be at least 30 MHz. In addition, only integer divisors should be used to achieve the 60 MHz USB clock source. Fractional divisors may increase jitter and compromise USB function.
USBCC is shown in Figure 27-92 and described in Table 27-99.
Return to Summary Table.
Figure 27-92 USBCC Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
CLKEN |
CSD |
| R-0x0 |
R/W-0x0 |
R/W-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
CLKDIV |
| R-0x0 |
R/W-0x0 |
|
Table 27-99 USBCC Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-10 |
RESERVED |
R |
0x0 |
|
| 9 |
CLKEN |
R/W |
0x0 |
USB Clock Enable.
This bit enables the 60 MHz clock used for the USB PHY.
This bit must always be set when using the USB, regardless of whether the PHY is internal or external.
0x0 = USB clock is disabled.
0x1 = USB clock is enabled.
|
| 8 |
CSD |
R/W |
0x0 |
Clock Source/Direction.
This bit specifies the source of the 60 MHz USB PHY clock when using ULPI.
0x0 = Internal Source. USB0CLK is an output to the external ULPI PHY and is configured using the following equation:
PLL_VCO/(CLKDIV + 1)
0x1 = External Source. USB0CLK is an input from the ULPI external PHY.
|
| 7-4 |
RESERVED |
R |
0x0 |
|
| 3-0 |
CLKDIV |
R/W |
0x0 |
PLL Clock Divisor.
This field specifies the divisor used to reduce the PLL VCO output to the 60 MHz clock source required for the serialization and deserialization module of the USB controller.
The divisor value is the CLKDIV value plus 1. |