27.5.14 USBCCONF Register (Offset = 0x61) [reset = 0x0]
USB Common Configuration (USBCCONF)
OTG A / Host
OTG B / Device
The USBCCONF register is an 8-bit register that contains various common configuration bits. These bits include the RX/TX early DMA enable bits.
USBCCONF is shown in Figure 27-19 and described in Table 27-24.
Return to Summary Table.
Figure 27-19 USBCCONF Register
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
TXEDMA |
RXEDMA |
| R-0x0 |
R/W-0x0 |
R/W-0x0 |
|
Table 27-24 USBCCONF Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 7-2 |
RESERVED |
R |
0x0 |
|
| 1 |
TXEDMA |
R/W |
0x0 |
TX Early DMA Enable.
0x0 = Late Mode: DMAREQ signal for all IN endpoints is deasserted when the MAXP bytes have been written to an endpoint.
0x1 = Early Mode: DMAREQ signal for all IN endpoints is deasserted when MAXP-8 bytes have been written to an endpoint.
|
| 0 |
RXEDMA |
R/W |
0x0 |
TX Early DMA Enable.
0x0 = Late Mode: DMAREQ signal for all OUT endpoints is deasserted when the MAXP bytes have been read to an endpoint.
0x1 = Early Mode: DMAREQ signal for all OUT endpoints is deasserted when MAXP-8 bytes have been read to an endpoint.
|