| 7 |
NAKTO |
R/W |
0x0 |
NAK Time-out.
Software must clear this bit to allow the endpoint to continue.
0x0 = No time-out.
0x1 = Indicates that endpoint 0 is halted following the receipt of NAK responses for longer than the time set by the USBNAKLMT register.
|
| 6 |
STATUS |
R/W |
0x0 |
STATUS Packet.
Setting this bit ensures that the DT bit is set in the USBCSRH0 register so that a DATA1 packet is used for the STATUS stage transaction.
This bit is automatically cleared when the STATUS stage is over.
0x0 = No transaction.
0x1 = Initiates a STATUS stage transaction. This bit must be set at the same time as the TXRDY or REQPKT bit is set.
|
| 5 |
REQPKT |
R/W |
0x0 |
Request Packet.
This bit is cleared when the RXRDY bit is set.
0x0 = No request.
0x1 = Requests an IN transaction.
|
| 4 |
ERROR |
R/W |
0x0 |
Error.
Software must clear this bit.
0x0 = No error.
0x1 = Three attempts have been made to perform a transaction with no response from the peripheral. The EP0 bit in the USBTXIS register is also set in this situation.
|
| 3 |
SETUP |
R/W |
0x0 |
Setup Packet.
Setting this bit always clears the DT bit in the USBCSRH0 register to send a DATA0 packet.
0x0 = Sends an OUT token.
0x1 = Sends a SETUP token instead of an OUT token for the transaction. This bit should be set at the same time as the TXRDY bit is set.
|
| 2 |
STALLED |
R/W |
0x0 |
Endpoint Stalled.
Software must clear this bit.
0x0 = No handshake has been received.
0x1 = A STALL handshake has been received.
|
| 1 |
TXRDY |
R/W |
0x0 |
Transmit Packet Ready.
This bit is cleared automatically when the data packet has been transmitted.
0x0 = No transmit packet is ready.
0x1 = Software sets this bit after loading a data packet into the TX FIFO. The EP0 bit in the USBTXIS register is also set in this situation.
If both the TXRDY and SETUP bits are set, a setup packet is sent. If just TXRDY is set, an OUT packet is sent.
|
| 0 |
RXRDY |
R/W |
0x0 |
Receive Packet Ready.
Software must clear this bit after the packet has been read from the FIFO to acknowledge that the data has been read from the FIFO.
0x0 = No received packet has been received.
0x1 = Indicates that a data packet has been received in the RX FIFO. The EP0 bit in the USBTXIS register is also set in this situation.
|