SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
USB Device RESUME Interrupt Status and Clear (USBDRISC)
OTG A / Host
OTG B / Device
The USBDRISC 32-bit register is the interrupt clear register. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.
USBDRISC is shown in Figure 27-84 and described in Table 27-91.
Return to Summary Table.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0x0 | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0x0 | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESUME | ||||||
R-0x0 | R/W1C-0x0 | ||||||