SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
USB Full-Speed Last Transaction to End of Frame Timing (USBFSEOF)
OTG A / Host
OTG B / Device
This 8-bit configuration register specifies the minimum time gap allowed between the start of the last transaction and the EOF for full-speed transactions.
USBFSEOF is shown in Figure 27-31 and described in Table 27-36.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FSEOFG | |||||||
R/W-0x77 | |||||||