SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
USB High Speed to UTM Operating Delay (USBHHSRTN)
OTG A / Host
OTG B / Device
This register sets the delay from the end of High Speed resume signaling (acting as a Host) to enable the UTM normal operating mode. This number when multiplied by 4 represents the number of SYSCLK cycles before the time-out occurs. That is, if SYSCLK is 30MHz, this number represents the number of 33.3 ns time intervals before the time-out occurs. If SYSCLK is 60MHz, this number represents the number of 16.7ns time intervals before the time-out occurs. Although this bit is written by the host in the CLK domain, the counter that utilizes this value is in the SYSCLK domain. No time domain crossing is provided as the value in this register is a static.
USBHHSRTN is shown in Figure 27-69 and described in Table 27-76.
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| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HHSRTN | |||||||||||||||
| R/W-0x0 | |||||||||||||||