SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
USB High Speed Time-out Adder (USBHSBT)
OTG A / Host
OTG B / Device
A high-speed host or device expecting a response to a transmission must not time-out the transaction if the interpacket delay is less than 736 bit times, and it must time-out the transaction if no signaling is seen within 816 bit times. This register represents the value to be added to the minimum high speed time-out period of 736 bit times. The time-out period can be increased in increments of 64 high speed bit times (133 ns). There are 16 possible values. By default, the adder is 0 thus setting the high speed time-out to its minimum value. Use of this register will allow the high speed time-out to be set to values that are greater than the maximum specified in USB 2.0 making the USB non-compliant.
USBHSBT is shown in Figure 27-70 and described in Table 27-77.
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| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0x0 | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | HSBT | ||||||
| R-0x0 | R/W-0x0 | ||||||