27.5.8 USBIE Register (Offset = 0xB) [reset = 0x6]
USB Interrupt Enable (USBIE)
OTG A / Host
OTG B / Device
USBIE is an 8-bit register that provides interrupt enable bits for each of the interrupts in USBIS. At reset interrupts 1 and 2 are enabled in Device mode.
USBIE for OTG A / Host is shown in Figure 27-11 and described in Table 27-16.
USBIE for OTG B / Device is shown in Figure 27-12 and described in Table 27-17.
Return to Summary Table.
Figure 27-11 USBIE Register (OTG A / Host)
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| VBUSERR |
SESREQ |
DISCON |
CONN |
SOF |
BABBLE |
RESUME |
RESERVED |
| R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x1 |
R/W-0x1 |
R-0x0 |
|
Table 27-16 USBIE Register Field Descriptions (OTG A / Host)
| Bit |
Field |
Type |
Reset |
Description |
| 7 |
VBUSERR |
R/W |
0x0 |
Enable VBUS Error Interrupt.
0x0 = The VBUSERR interrupt is suppressed and not sent to the interrupt controller.
0x1 = An interrupt is sent to the interrupt controller when the VBUSERR bit in the USBIS register is set.
|
| 6 |
SESREQ |
R/W |
0x0 |
Enable Session Request.
0x0 = The SESREQ interrupt is suppressed and not sent to the interrupt controller.
0x1 = An interrupt is sent to the interrupt controller when the SESREEQ bit in the USBIS register is set.
|
| 5 |
DISCON |
R/W |
0x0 |
Enable Disconnect Interrupt.
0x0 = The DISCON interrupt is suppressed and not sent to the interrupt controller.
0x1 = An interrupt is sent to the interrupt controller when the DISCON bit in the USBIS register is set.
|
| 4 |
CONN |
R/W |
0x0 |
Enable Connect Interrupt.
0x0 = The CONN interrupt is suppressed and not sent to the interrupt controller.
0x1 = An interrupt is sent to the interrupt controller when the CONN bit in the USBIS register is set.
|
| 3 |
SOF |
R/W |
0x0 |
Enable Start-of-Frame Interrupt.
0x0 = The SOF interrupt is suppressed and not sent to the interrupt controller.
0x1 = An interrupt is sent to the interrupt controller when the SOF bit in the USBIS register is set.
|
| 2 |
BABBLE |
R/W |
0x1 |
Enable Babble Interrupt.
0x0 = The BABBLE interrupt is suppressed and not sent to the interrupt controller.
0x1 = An interrupt is sent to the interrupt controller when the BABBLE bit in the USBIS register is set.
|
| 1 |
RESUME |
R/W |
0x1 |
Enable RESUME Interrupt.
0x0 = The RESUME interrupt is suppressed and not sent to the interrupt controller.
0x1 = An interrupt is sent to the interrupt controller when the RESUME bit in the USBIS register is set.
|
| 0 |
RESERVED |
R |
0x0 |
|
Figure 27-12 USBIE Register (OTG B / Device)
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
DISCON |
RESERVED |
SOF |
RESET |
RESUME |
SUSPEND |
| R-0x0 |
R/W-0x0 |
R-0x0 |
R/W-0x0 |
R/W-0x1 |
R/W-0x1 |
R/W-0x0 |
|
Table 27-17 USBIE Register Field Descriptions (OTG B / Device)
| Bit |
Field |
Type |
Reset |
Description |
| 7-6 |
RESERVED |
R |
0x0 |
|
| 5 |
DISCON |
R/W |
0x0 |
Enable Disconnect Interrupt.
0x0 = The DISCON interrupt is suppressed and not sent to the interrupt controller.
0x1 = An interrupt is sent to the interrupt controller when the DISCON bit in the USBIS register is set.
|
| 4 |
RESERVED |
R |
0x0 |
|
| 3 |
SOF |
R/W |
0x0 |
Enable Start-of-Frame Interrupt.
0x0 = The SOF interrupt is suppressed and not sent to the interrupt controller.
0x1 = An interrupt is sent to the interrupt controller when the SOF bit in the USBIS register is set.
|
| 2 |
RESET |
R/W |
0x1 |
Enable RESET Interrupt.
0x0 = The RESET interrupt is suppressed and not sent to the interrupt controller.
0x1 = An interrupt is sent to the interrupt controller when the RESET bit in the USBIS register is set.
|
| 1 |
RESUME |
R/W |
0x1 |
Enable RESUME Interrupt.
0x0 = The RESUME interrupt is suppressed and not sent to the interrupt controller.
0x1 = An interrupt is sent to the interrupt controller when the RESUME bit in the USBIS register is set.
|
| 0 |
SUSPEND |
R/W |
0x0 |
Enable SUSPEND Interrupt.
0x0 = The SUSPEND interrupt is suppressed and not sent to the interrupt controller.
0x1 = An interrupt is sent to the interrupt controller when the SUSPEND bit in the USBIS register is set.
|