27.5.60 USBLPMATTR Register (Offset = 0x360) [reset = 0x0]
USB LPM Attributes (USBLPMATTR)
OTG A / Host
OTG B / Device
This register is used to define the attributes of an LPM transaction and sleep cycle. In both the Host mode and the Peripheral mode, the meaning of this register is the same however the source of the data is different for Host and Peripheral as follows:
- Peripheral Mode: In Peripheral mode, the values in this register will contain the equivalent attributes that were received in the last LPM transaction that was accepted. This register is updated with the LPM packet contents if the response to the LPM transaction was an ACK. This register can be update through software. In all other cases, this register will hold its current value.
- Host Mode: In HOST mode software will set-up the values in this register to define the next LPM transaction that will be transmitted. These values will be inserted in the payload of the next LPM Transaction.
USBLPMATTR is shown in Figure 27-71 and described in Table 27-78.
Return to Summary Table.
Figure 27-71 USBLPMATTR Register
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| ENDPT |
RESERVED |
RMTWAK |
| R-0x0 |
R-0x0 |
R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| HIRD |
LINKSTATE |
| R-0x0 |
R/W-0x0 |
|
Table 27-78 USBLPMATTR Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 15-12 |
ENDPT |
R |
0x0 |
Endpoint.
This is the Endpoint in the Token Packet of the LPM transaction. |
| 11-9 |
RESERVED |
R |
0x0 |
|
| 8 |
RMTWAK |
R |
0x0 |
Remote Wake.
This bit is applied on a temporary basis only and only to the current suspend state.
After the current suspend cycle, the remote wakeup capability that was negotiated upon enumeration applies.
0x0 = Remote wakeup is not enabled.
0x1 = Remote wakeup is enabled.
|
| 7-4 |
HIRD |
R |
0x0 |
Host Initiated Resume Duration.
This value is the minimum time the host drives resume on the Bus.
The value in this register corresponds to an actual resume time of:
Resume Time = 50 µs + HIRD * 75 µs
This results in a range from 50 µs to 1200 us. |
| 3-0 |
LINKSTATE |
R/W |
0x0 |
Link State.
This value is provided by the host to the peripheral to indicate what state the peripheral must transition to after the receipt and acceptance of a LPM transaction.
0x0 = RESERVED
0x1 = Sleep State (L1)
|