27.5.43 USBRXCSRLn Register [reset = 0x0]
USB Receive Control and Status Endpoint 1 Low (USBRXCSRL1), offset 0x116
USB Receive Control and Status Endpoint 2 Low (USBRXCSRL2), offset 0x126
USB Receive Control and Status Endpoint 3 Low (USBRXCSRL3), offset 0x136
USB Receive Control and Status Endpoint 4 Low (USBRXCSRL4), offset 0x146
USB Receive Control and Status Endpoint 5 Low (USBRXCSRL5), offset 0x156
USB Receive Control and Status Endpoint 6 Low (USBRXCSRL6), offset 0x166
USB Receive Control and Status Endpoint 7 Low (USBRXCSRL7), offset 0x176
OTG A / Host
OTG B / Device
USBRXCSRLn is an 8-bit register that provides control and status bits for transfers through the currently selected receive endpoint.
USBRXCSRLn for OTG A / Host is shown in Figure 27-52 and described in Table 27-57.
USBRXCSRLn for OTG B / Device is shown in Figure 27-53 and described in Table 27-58.
Return to Summary Table.
Figure 27-52 USBRXCSRLn Register (OTG A / Host)
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| CLRDT |
STALLED |
REQPKT |
FLUSH |
DATAERR/NAKTO |
ERROR |
FULL |
RXRDY |
| W1C-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R-0x0 |
R/W-0x0 |
|
Table 27-57 USBRXCSRLn Register Field Descriptions (OTG A / Host)
| Bit |
Field |
Type |
Reset |
Description |
| 7 |
CLRDT |
W1C |
0x0 |
Clear Data Toggle.
Writing a 1 to this bit clears the DT bit in the USBRXCSRHn register. |
| 6 |
STALLED |
R/W |
0x0 |
Endpoint Stalled.
Software must clear this bit.
0x0 = A STALL handshake has not been received.
0x1 = A STALL handshake has been received. The EPn bit in the USBRXIS register is also set.
|
| 5 |
REQPKT |
R/W |
0x0 |
Request Packet.
This bit is cleared when RXRDY is set.
0x0 = No request.
0x1 = Requests an IN transaction.
|
| 4 |
FLUSH |
R/W |
0x0 |
Flush FIFO.
Note that if the FIFO is double-buffered, FLUSH may have to be set twice to completely clear the FIFO.
This bit should only be set when the RXRDY bit is set.
At other times, it may cause data to be corrupted.
0x0 = No effect.
0x1 = Flushes the next packet to be read from the endpoint receive FIFO. The FIFO pointer is reset and the RXRDY bit is cleared.
|
| 3 |
DATAERR/NAKTO |
R/W |
0x0 |
Data Error / NAK Time-out.
0x0 = Normal operation.
0x1 = Isochronous endpoints only:
Indicates that RXRDY is set and the data packet has a CRC or bit-stuff error. This bit is cleared when RXRDY is cleared.
Bulk endpoints only:
Indicates that the receive endpoint is halted following the receipt of NAK responses for longer than the time set by the NAKLMT field in the USBRXINTERVALn register.
Software must clear this bit to allow the endpoint to continue.
|
| 2 |
ERROR |
R/W |
0x0 |
Error.
Software must clear this bit.
This bit is only valid when the receive endpoint is operating in Bulk or Interrupt mode.
In Isochronous mode, it always returns zero.
0x0 = No error.
0x1 = Three attempts have been made to receive a packet and no data packet has been received. The EPn bit in the USBRXIS register is set in this situation.
|
| 1 |
FULL |
R |
0x0 |
FIFO Full.
0x0 = The receive FIFO is not full.
0x1 = No more packets can be loaded into the receive FIFO.
|
| 0 |
RXRDY |
R/W |
0x0 |
Receive Packet Ready.
If the AUTOCLR bit in the USBRXCSRHn register is set, then the this bit is automatically cleared when a packet of USBRXMAXPn bytes has been unloaded from the receive FIFO.
If the AUTOCLR bit is clear, or if packets of less than the maximum packet size are unloaded, then software must clear this bit manually when the packet has been unloaded from the receive FIFO.
0x0 = No data packet has been received.
0x1 = A data packet has been received. The EPn bit in the USBRXIS register is also set in this situation.
|
Figure 27-53 USBRXCSRLn Register (OTG B / Device)
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| CLRDT |
STALLED |
STALL |
FLUSH |
DATAERR |
OVER |
FULL |
RXRDY |
| W1C-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R-0x0 |
R/W-0x0 |
R-0x0 |
R/W-0x0 |
|
Table 27-58 USBRXCSRLn Register Field Descriptions (OTG B / Device)
| Bit |
Field |
Type |
Reset |
Description |
| 7 |
CLRDT |
W1C |
0x0 |
Clear Data Toggle.
Writing a 1 to this bit clears the DT bit in the USBRXCSRHn register. |
| 6 |
STALLED |
R/W |
0x0 |
Endpoint Stalled.
Software must clear this bit.
0x0 = A STALL handshake has not been transmitted.
0x1 = A STALL handshake has been transmitted.
|
| 5 |
STALL |
R/W |
0x0 |
Send STALL.
Software must clear this bit to terminate the STALL condition.
This bit has no effect where the endpoint is being used for isochronous transfers.
0x0 = No effect.
0x1 = Issues a STALL handshake.
|
| 4 |
FLUSH |
R/W |
0x0 |
Flush FIFO.
The CPU writes a 1 to this bit to flush the next packet to be read from the endpoint receive FIFO. The FIFO pointer is reset and the RXRDY bit is cleared.
Note that if the FIFO is double-buffered, FLUSH may have to be set twice to completely clear the FIFO.
This bit should only be set when the RXRDY bit is set. At other times, it may cause data to be corrupted.
0x0 = No effect.
0x1 = Flushes the next packet from the endpoint receive FIFO. The FIFO pointer is reset and the RXRDY bit is cleared.
|
| 3 |
DATAERR |
R |
0x0 |
Data Error.
This bit is cleared when RXRDY is cleared.
This bit is only valid when the endpoint is operating in Isochronous mode. In Bulk mode, it always returns zero.
0x0 = Normal operation.
0x1 = Indicates that RXRDY is set and the data packet has a CRC or bit-stuff error.
|
| 2 |
OVER |
R/W |
0x0 |
Overrun.
Software must clear this bit.
This bit is only valid when the endpoint is operating in Isochronous mode. In Bulk mode, it always returns zero.
0x0 = No overrun error.
0x1 = Indicates that an OUT packet cannot be loaded into the receive FIFO.
|
| 1 |
FULL |
R |
0x0 |
FIFO Full.
0x0 = The receive FIFO is not full.
0x1 = No more packets can be loaded into the receive FIFO.
|
| 0 |
RXRDY |
R/W |
0x0 |
Receive Packet Ready.
If the AUTOCLR bit in the USBRXCSRHn register is set, then the this bit is automatically cleared when a packet of USBRXMAXPn bytes has been unloaded from the receive FIFO.
If the AUTOCLR bit is clear, or if packets of less than the maximum packet size are unloaded, then software must clear this bit manually when the packet has been unloaded from the receive FIFO.
0x0 = No data packet has been received.
0x1 = A data packet has been received. The EPn bit in the USBRXIS register is also set in this situation.
|