27.5.55 USBRXDPKTBUFDIS Register (Offset = 0x340) [reset = 0x0]
USB Receive Double Packet Buffer Disable (USBRXDPKTBUFDIS)
OTG A / Host
OTG B / Device
USBRXDPKTBUFDIS is a 16-bit register that indicates which of the receive endpoints have disabled the double-packet buffer functionality (see Section 27.3.1.3.2).
USBRXDPKTBUFDIS is shown in Figure 27-66 and described in Table 27-73.
Return to Summary Table.
Figure 27-66 USBRXDPKTBUFDIS Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
EP7 |
EP6 |
EP5 |
EP4 |
EP3 |
EP2 |
EP1 |
RESERVED |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R-0x0 |
|
Table 27-73 USBRXDPKTBUFDIS Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7 |
EP7 |
R/W |
0x0 |
EP7 RX Double-Packet Buffer Disable.
0x0 = Disables double-packet buffering.
0x1 = Enables double-packet buffering.
|
6 |
EP6 |
R/W |
0x0 |
EP6 RX Double-Packet Buffer Disable.
0x0 = Disables double-packet buffering.
0x1 = Enables double-packet buffering.
|
5 |
EP5 |
R/W |
0x0 |
EP5 RX Double-Packet Buffer Disable.
0x0 = Disables double-packet buffering.
0x1 = Enables double-packet buffering.
|
4 |
EP4 |
R/W |
0x0 |
EP4 RX Double-Packet Buffer Disable.
0x0 = Disables double-packet buffering.
0x1 = Enables double-packet buffering.
|
3 |
EP3 |
R/W |
0x0 |
EP3 RX Double-Packet Buffer Disable.
0x0 = Disables double-packet buffering.
0x1 = Enables double-packet buffering.
|
2 |
EP2 |
R/W |
0x0 |
EP2 RX Double-Packet Buffer Disable.
0x0 = Disables double-packet buffering.
0x1 = Enables double-packet buffering.
|
1 |
EP1 |
R/W |
0x0 |
EP1 RX Double-Packet Buffer Disable.
0x0 = Disables double-packet buffering.
0x1 = Enables double-packet buffering.
|
0 |
RESERVED |
R |
0x0 |
|