27.5.6 USBRXIE Register (Offset = 0x8) [reset = 0xFE]
USB Receive Interrupt Enable (USBRXIE)
OTG A / Host
OTG B / Device
USBRXIE is a 16-bit register that provides interrupt enable bits for the interrupts in the USBRXIS register. When a bit is set, the USB interrupt is asserted to the interrupt controller when the corresponding interrupt bit in the USBRXIS register is set. When a bit is cleared, the interrupt in the USBRXIS register is still set but the USB interrupt to the interrupt controller is not asserted. On reset, all interrupts are enabled.
USBRXIE is shown in Figure 27-8 and described in Table 27-13.
Return to Summary Table.
Figure 27-8 USBRXIE Register
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| EP7 |
EP6 |
EP5 |
EP4 |
EP3 |
EP2 |
EP1 |
RESERVED |
| R/W-0x1 |
R/W-0x1 |
R/W-0x1 |
R/W-0x1 |
R/W-0x1 |
R/W-0x1 |
R/W-0x1 |
R-0x0 |
|
Table 27-13 USBRXIE Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 7 |
EP7 |
R/W |
0x1 |
RX Endpoint 7 Interrupt Enable.
0x0 = The EP7 receive interrupt is suppressed and not sent to the interrupt controller.
0x1 = An interrupt is sent to the interrupt controller when the EP7 bit in the USBRXIS register is set.
|
| 6 |
EP6 |
R/W |
0x1 |
RX Endpoint 6 Interrupt Enable.
Same description as EP7. |
| 5 |
EP5 |
R/W |
0x1 |
RX Endpoint 5 Interrupt Enable.
Same description as EP7. |
| 4 |
EP4 |
R/W |
0x1 |
RX Endpoint 4 Interrupt Enable.
Same description as EP7. |
| 3 |
EP3 |
R/W |
0x1 |
RX Endpoint 3 Interrupt Enable.
Same description as EP7. |
| 2 |
EP2 |
R/W |
0x1 |
RX Endpoint 2 Interrupt Enable.
Same description as EP7. |
| 1 |
EP1 |
R/W |
0x1 |
RX Endpoint 1 Interrupt Enable.
Same description as EP7. |
| 0 |
RESERVED |
R |
0x0 |
|