SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
USB Host Receive Polling Interval Endpoint 1 (USBRXINTERVAL1), offset 0x11D
USB Host Receive Polling Interval Endpoint 2 (USBRXINTERVAL2), offset 0x12D
USB Host Receive Polling Interval Endpoint 3 (USBRXINTERVAL3), offset 0x13D
USB Host Receive Polling Interval Endpoint 4 (USBRXINTERVAL4), offset 0x14D
USB Host Receive Polling Interval Endpoint 5 (USBRXINTERVAL5), offset 0x15D
USB Host Receive Polling Interval Endpoint 6 (USBRXINTERVAL6), offset 0x16D
USB Host Receive Polling Interval Endpoint 7 (USBRXINTERVAL7), offset 0x17D
OTG A / Host
USBRXINTERVALn is an 8-bit register that, for interrupt and isochronous transfers, defines the polling interval for the currently selected receive endpoint. For bulk endpoints, this register defines the number of frames after which the endpoint should time out on receiving a stream of NAK responses.
The USBRXINTERVALn register value defines a number of frames:
Transfer Type | Speed | Valid values (m) | Interpretation |
---|---|---|---|
Interrupt | Low Speed or Full Speed | 0x01 to 0xFF | The polling interval is m frames. |
Interrupt | High Speed | 0x01 to 0x10 | Polling interval is 2(m-1) microframes. |
Isochronous | Full Speed or High Speed | 0x01 to 0x10 | The polling interval is 2(m-1)frames/microframes. |
Bulk | Full-Speed or High Speed | 0x02 to 0x10 | The NAK Limit is 2(m-1) frames/microframes. A value of 0 or 1 disables the NAK time-out function. |
USBRXINTERVALn is shown in Figure 27-60 and described in Table 27-67.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXPOLL/NAKLMT | |||||||
R/W-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | TXPOLL/NAKLMT | R/W | 0x0 | RX Polling / NAK Limit.
The polling interval for interrupt/isochronous transfers or the NAK limit for bulk transfers. See Table 27-66 for valid entries; other values are Reserved. |