SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
USB Maximum Receive Data Endpoint 1 (USBRXMAXP1), offset 0x114
USB Maximum Receive Data Endpoint 2 (USBRXMAXP2), offset 0x124
USB Maximum Receive Data Endpoint 3 (USBRXMAXP3), offset 0x134
USB Maximum Receive Data Endpoint 4 (USBRXMAXP4), offset 0x144
USB Maximum Receive Data Endpoint 5 (USBRXMAXP5), offset 0x154
USB Maximum Receive Data Endpoint 6 (USBRXMAXP6), offset 0x164
USB Maximum Receive Data Endpoint 7 (USBRXMAXP7), offset 0x174
OTG A / Host
OTG B / Device
The USBRXMAXPn is a 16-bit register which defines the maximum amount of data that can be transferred through the selected receive endpoint in a single operation.
Bits 10:0 define (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for bulk, interrupt and isochronous transfers in full-speed operations.
The total amount of data represented by the value written to this register must not exceed the FIFO size for the receive endpoint, and must not exceed half the FIFO size if double-buffering is required.
NOTE
USBRXMAXPn must be set to an even number of bytes for proper interrupt generation in USB DMA Basic mode.
USBRXMAXPn is shown in Figure 27-51 and described in Table 27-56.
Return to Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | MAXLOAD | ||||||
| R-0x0 | R/W-0x0 | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MAXLOAD | |||||||
| R/W-0x0 | |||||||