27.5.41 USBTXCSRHn Register [reset = 0x0]
USB Transmit Control and Status Endpoint 1 High (USBTXCSRH1), offset 0x113
USB Transmit Control and Status Endpoint 2 High (USBTXCSRH2), offset 0x123
USB Transmit Control and Status Endpoint 3 High (USBTXCSRH3), offset 0x133
USB Transmit Control and Status Endpoint 4 High (USBTXCSRH4), offset 0x143
USB Transmit Control and Status Endpoint 5 High (USBTXCSRH5), offset 0x153
USB Transmit Control and Status Endpoint 6 High (USBTXCSRH6), offset 0x163
USB Transmit Control and Status Endpoint 7 High (USBTXCSRH7), offset 0x173
OTG A / Host
OTG B / Device
USBTXCSRHn is an 8-bit register that provides additional control for transfers through the currently selected transmit endpoint.
USBTXCSRHn for OTG A / Host is shown in Figure 27-49 and described in Table 27-54.
USBTXCSRHn for OTG B / Device is shown in Figure 27-50 and described in Table 27-55.
Return to Summary Table.
Figure 27-49 USBTXCSRHn Register (OTG A / Host)
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| AUTOSET |
RESERVED |
MODE |
DMAEN |
FDT |
DMAMOD |
DTWE |
DT |
| R/W-0x0 |
R-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
|
Table 27-54 USBTXCSRHn Register Field Descriptions (OTG A / Host)
| Bit |
Field |
Type |
Reset |
Description |
| 7 |
AUTOSET |
R/W |
0x0 |
Auto Set.
0x0 = The TXRDY bit must be set manually.
0x1 = Enables the TXRDY bit to be automatically set when data of the maximum packet size (value in USBTXMAXPn) is loaded into the transmit FIFO. If a packet of less than the maximum packet size is loaded, then the TXRDY bit must be set manually.
|
| 6 |
RESERVED |
R |
0x0 |
|
| 5 |
MODE |
R/W |
0x0 |
Mode.
This bit only has an effect when the same endpoint FIFO is used for both transmit and receive transactions.
0x0 = Enables the endpoint direction as RX.
0x1 = Enables the endpoint direction as TX.
|
| 4 |
DMAEN |
R/W |
0x0 |
DMA Request Enable.
0x0 = Disables the DMA request for the transmit endpoint.
0x1 = Enables the DMA request for the transmit endpoint.
|
| 3 |
FDT |
R/W |
0x0 |
Force Data Toggle.
0x0 = No effect.
0x1 = Forces the endpoint DT bit to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This bit can be used by interrupt transmit endpoints that are used to communicate rate feedback for isochronous endpoints.
|
| 2 |
DMAMOD |
R/W |
0x0 |
DMA Request Mode.
This bit must not be cleared either before or in the same cycle as the above DMAEN bit is cleared.
0x0 = An interrupt is generated after every DMA packet transfer.
0x1 = An interrupt is generated only after the entire DMA transfer is complete.
|
| 1 |
DTWE |
R/W |
0x0 |
Data Toggle Write Enable.
This bit is automatically cleared once the new value is written.
0x0 = The DT bit cannot be written.
0x1 = Enables the current state of the transmit endpoint data to be written (see DT bit).
|
| 0 |
DT |
R/W |
0x0 |
Data Toggle.
When read, this bit indicates the current state of the transmit endpoint data toggle.
If DTWE is High, this bit may be written with the required setting of the data toggle.
If DTWE is Low, any value written to this bit is ignored.
Care should be taken when writing to this bit as it should only be changed to RESET the transmit endpoint. |
Figure 27-50 USBTXCSRHn Register (OTG B / Device)
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| AUTOSET |
ISO |
MODE |
DMAEN |
FDT |
DMAMOD |
RESERVED |
| R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R-0x0 |
|
Table 27-55 USBTXCSRHn Register Field Descriptions (OTG B / Device)
| Bit |
Field |
Type |
Reset |
Description |
| 7 |
AUTOSET |
R/W |
0x0 |
Auto Set.
0x0 = The TXRDY bit must be set manually.
0x1 = Enables the TXRDY bit to be automatically set when data of the maximum packet size (value in USBTXMAXPn) is loaded into the transmit FIFO. If a packet of less than the maximum packet size is loaded, then the TXRDY bit must be set manually.
|
| 6 |
ISO |
R/W |
0x0 |
Isochronous Transfers.
0x0 = Enables the transmit endpoint for bulk or interrupt transfers.
0x1 = Enables the transmit endpoint for isochronous transfers.
|
| 5 |
MODE |
R/W |
0x0 |
Mode.
This bit only has an effect where the same endpoint FIFO is used for both transmit and receive transactions.
0x0 = Enables the endpoint direction as RX.
0x1 = Enables the endpoint direction as TX.
|
| 4 |
DMAEN |
R/W |
0x0 |
DMA Request Enable.
0x0 = Disables the DMA request for the transmit endpoint.
0x1 = Enables the DMA request for the transmit endpoint.
|
| 3 |
FDT |
R/W |
0x0 |
Force Data Toggle.
0x0 = No effect.
0x1 = Forces the endpoint DT bit to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This bit can be used by interrupt transmit endpoints that are used to communicate rate feedback for isochronous endpoints.
|
| 2 |
DMAMOD |
R/W |
0x0 |
DMA Request Mode.
This bit must not be cleared either before or in the same cycle as the above DMAEN bit is cleared.
0x0 = An interrupt is generated after every DMA packet transfer.
0x1 = An interrupt is generated only after the entire DMA transfer is complete.
|
| 1-0 |
RESERVED |
R |
0x0 |
|