27.5.40 USBTXCSRLn Register [reset = 0x0]
USB Transmit Control and Status Endpoint 1 Low (USBTXCSRL1), offset 0x112
USB Transmit Control and Status Endpoint 2 Low (USBTXCSRL2), offset 0x122
USB Transmit Control and Status Endpoint 3 Low (USBTXCSRL3), offset 0x132
USB Transmit Control and Status Endpoint 4 Low (USBTXCSRL4), offset 0x142
USB Transmit Control and Status Endpoint 5 Low (USBTXCSRL5), offset 0x152
USB Transmit Control and Status Endpoint 6 Low (USBTXCSRL6), offset 0x162
USB Transmit Control and Status Endpoint 7 Low (USBTXCSRL7), offset 0x172
OTG A / Host
OTG B / Device
USBTXCSRLn is an 8-bit register that provides control and status bits for transfers through the currently selected transmit endpoint.
USBTXCSRLn for OTG A / Host is shown in Figure 27-47 and described in Table 27-52.
USBTXCSRLn for OTG B / Device is shown in Figure 27-48 and described in Table 27-53.
Return to Summary Table.
Figure 27-47 USBTXCSRLn Register (OTG A / Host)
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| NAKTO |
CLRDT |
STALLED |
SETUP |
FLUSH |
ERROR |
FIFONE |
TXRDY |
| R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
|
Table 27-52 USBTXCSRLn Register Field Descriptions (OTG A / Host)
| Bit |
Field |
Type |
Reset |
Description |
| 7 |
NAKTO |
R/W |
0x0 |
NAK Time-out.
0x0 = No time-out.
0x1 = Bulk endpoints only:
Indicates that the transmit endpoint is halted following the receipt of NAK responses for longer than the time set by the NAKLMT field in the USBTXINTERVALn register.
Software must clear this bit to allow the endpoint to continue.
|
| 6 |
CLRDT |
R/W |
0x0 |
Clear Data Toggle.
Writing a 1 to this bit clears the DT bit in the USBTXCSRHn register. |
| 5 |
STALLED |
R/W |
0x0 |
Endpoint Stalled.
Software must clear this bit.
0x0 = A STALL handshake has not been received.
0x1 = Indicates that a STALL handshake has been received. When this bit is set, any USB DMA request that is in progress is stopped, the FIFO is completely flushed, and the TXRDY bit is cleared.
|
| 4 |
SETUP |
R/W |
0x0 |
Setup Packet.
Setting this bit also clears the DT bit in the USBTXCSRHn register.
0x0 = No SETUP token is sent.
0x1 = Sends a SETUP token instead of an OUT token for the transaction. This bit should be set at the same time as the TXRDY bit is set.
|
| 3 |
FLUSH |
R/W |
0x0 |
Flush FIFO.
This bit may be set simultaneously with the TXRDY bit to abort the packet that is currently being loaded into the FIFO.
Note that if the FIFO is double-buffered, FLUSH may have to be set twice to completely clear the FIFO.
This bit should only be set when the TXRDY bit is clear.
At other times, it may cause data to be corrupted.
0x0 = No effect.
0x1 = Flushes the latest packet from the endpoint transmit FIFO. The FIFO pointer is reset and the TXRDY bit is cleared. The EPn bit in the USBTXIS register is also set in this situation.
|
| 2 |
ERROR |
R/W |
0x0 |
Error.
Software must clear this bit.
This is valid only when the endpoint is operating in Bulk or Interrupt mode.
0x0 = No error.
0x1 = Three attempts have been made to send a packet and no handshake packet has been received. The TXRDY bit is cleared, the EPn bit in the USBTXIS register is set, and the FIFO is completely flushed in this situation.
|
| 1 |
FIFONE |
R/W |
0x0 |
FIFO Not Empty.
0x0 = The FIFO is empty.
0x1 = At least one packet is in the transmit FIFO.
|
| 0 |
TXRDY |
R/W |
0x0 |
Transmit Packet Ready.
This bit is cleared automatically when a data packet has been transmitted.
The EPn bit in the USBTXIS register is also set at this point.
TXRDY is also automatically cleared prior to loading a second packet into a double-buffered FIFO.
0x0 = No transmit packet is ready.
0x1 = Software sets this bit after loading a data packet into the TX FIFO.
|
Figure 27-48 USBTXCSRLn Register (OTG B / Device)
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
CLRDT |
STALLED |
STALL |
FLUSH |
UNDRN |
FIFONE |
TXRDY |
| R-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
|
Table 27-53 USBTXCSRLn Register Field Descriptions (OTG B / Device)
| Bit |
Field |
Type |
Reset |
Description |
| 7 |
RESERVED |
R |
0x0 |
|
| 6 |
CLRDT |
R/W |
0x0 |
Clear Data Toggle.
Writing a 1 to this bit clears the DT bit in the USBTXCSRHn register. |
| 5 |
STALLED |
R/W |
0x0 |
Endpoint Stalled.
Software must clear this bit.
0x0 = A STALL handshake has not been transmitted.
0x1 = A STALL handshake has been transmitted. The FIFO is flushed and the TXRDY bit is cleared.
|
| 4 |
STALL |
R/W |
0x0 |
Send STALL.
Software clears this bit to terminate the STALL condition.
This bit has no effect in isochronous transfers.
0x0 = No effect.
0x1 = Issues a STALL handshake to an IN token.
|
| 3 |
FLUSH |
R/W |
0x0 |
Flush FIFO.
This bit may be set simultaneously with the TXRDY bit to abort the packet that is currently being loaded into the FIFO.
Note that if the FIFO is double-buffered, FLUSH may have to be set twice to completely clear the FIFO.
This bit should only be set when the TXRDY bit is clear.
At other times, it may cause data to be corrupted.
0x0 = No effect.
0x1 = Flushes the latest packet from the endpoint transmit FIFO. The FIFO pointer is reset and the TXRDY bit is cleared. The EPn bit in the USBTXIS register is also set in this situation.
|
| 2 |
UNDRN |
R/W |
0x0 |
Underrun.
Software must clear this bit.
0x0 = No underrun.
0x1 = An IN token has been received when TXRDY is not set.
|
| 1 |
FIFONE |
R/W |
0x0 |
FIFO Not Empty.
0x0 = The FIFO is empty.
0x1 = At least one packet is in the transmit FIFO.
|
| 0 |
TXRDY |
R/W |
0x0 |
Transmit Packet Ready.
This bit is cleared automatically when a data packet has been transmitted.
The EPn bit in the USBTXIS register is also set at this point.
TXRDY is also automatically cleared prior to loading a second packet into a double-buffered FIFO.
0x0 = No transmit packet is ready.
0x1 = Software sets this bit after loading a data packet into the TX FIFO.
|