27.5.5 USBTXIE Register (Offset = 0x6) [reset = 0xFF]
USB Transmit Interrupt Enable (USBTXIE)
OTG A / Host
OTG B / Device
USBTXIE is a 16-bit register that provides interrupt enable bits for the interrupts in the USBTXIS register. When a bit is set, the USB interrupt is asserted to the interrupt controller when the corresponding interrupt bit in the USBTXIS register is set. When a bit is cleared, the interrupt in the USBTXIS register is still set but the USB interrupt to the interrupt controller is not asserted. On reset, all interrupts are enabled.
USBTXIE is shown in Figure 27-7 and described in Table 27-12.
Return to Summary Table.
Figure 27-7 USBTXIE Register
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| EP7 |
EP6 |
EP5 |
EP4 |
EP3 |
EP2 |
EP1 |
EP0 |
| R/W-0x1 |
R/W-0x1 |
R/W-0x1 |
R/W-0x1 |
R/W-0x1 |
R/W-0x1 |
R/W-0x1 |
R/W-0x1 |
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Table 27-12 USBTXIE Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 7 |
EP7 |
R/W |
0x1 |
TX Endpoint 7 Interrupt Enable.
0x0 = The EP7 transmit interrupt is suppressed and not sent to the interrupt controller.
0x1 = An interrupt is sent to the interrupt controller when the EP7 bit in the USBTXIS register is set.
|
| 6 |
EP6 |
R/W |
0x1 |
TX Endpoint 6 Interrupt Enable.
Same description as EP7. |
| 5 |
EP5 |
R/W |
0x1 |
TX Endpoint 5 Interrupt Enable.
Same description as EP7. |
| 4 |
EP4 |
R/W |
0x1 |
TX Endpoint 4 Interrupt Enable.
Same description as EP7. |
| 3 |
EP3 |
R/W |
0x1 |
TX Endpoint 3 Interrupt Enable.
Same description as EP7. |
| 2 |
EP2 |
R/W |
0x1 |
TX Endpoint 2 Interrupt Enable.
Same description as EP7. |
| 1 |
EP1 |
R/W |
0x1 |
TX Endpoint 1 Interrupt Enable.
Same description as EP7. |
| 0 |
EP0 |
R/W |
0x1 |
TX and RX Endpoint 0 Interrupt Enable.
0x0 = The EP0 transmit and receive interrupt is suppressed and not sent to the interrupt controller.
0x1 = An interrupt is sent to the interrupt controller when the EP0 bit in the USBTXIS register is set.
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