SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
USB OTG VBUS Pulse Timing (USBVPLEN)
OTG
This 8-bit configuration register specifies the duration of the VBUS pulsing charge.
USBVPLEN is shown in Figure 27-29 and described in Table 27-34.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VPLEN | |||||||
R/W-0x3C | |||||||