SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The behavior of the DMA request line for an Rx Endpoint depends on the DMA Request Mode (DMAMOD) selected through the USB Receive Control and Status Endpoint n High (USBRXCSRHn) register. In DMA Request Mode 0, the Rx DMA request line is held high when a data packet is available in the endpoint FIFO and is low either when the last byte of the data packet has been read, or when the RXRDY bit in USB Receive Control and Status Endpoint n Low (USBRXCSRLn) is cleared. In DMA Request Mode 1, the DMA request line only goes high when the packet received is of the maximum packet size (as set in the USBRXMAXPn register). If the packet received is of some other size, the DMA request line stays low with the result that the packet remains in the FIFO with the RXRDY bit set. This causes an Rx Endpoint interrupt to be generated (if enabled).
The DMA Request Modes are primarily designed to be used where large packets of data are transferred to a Bulk endpoint. The USB protocol requires such packets to be split into a series of packets of maximum packet size (512 bytes for high speed, 64 bytes for full speed). The last packet in the series may be less than the maximum packet size (or a null packet if the total size of the transfer is an exact multiple of the maximum packet size) and the receiver may interpret this short packet as signaling the end of the transfer. DMA Request Mode 1 can be used, with a suitably programmed DMA controller, to avoid the overhead of having to interrupt the processor after each individual packet instead just interrupting the processor after the transfer has completed.
NOTE
If the Request Mode is switched from Request Mode 1 to Request Mode 0, the request line is asserted if there is a packet in the FIFO in order to allow this prereceived packet to be downloaded.