SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
For Tx endpoints, the DMA request line is high when the endpoint FIFO is able to accept a data packet, and goes low when MAXLOAD transmit bytes have been loaded into the FIFO. Alternatively, the request line is held low when the TXRDY bit in USBTXCSRLn register is set. To use DMA to send a large block of data to the USB host over a Bulk Tx endpoint, we recommend setting up the DMA controller and the USB as follows:
Programmed like this, the USB DMA request line is held high whenever there is space in its FIFO to accept a packet. Further, the TXRDY bit is automatically set after the DMA controller has loaded the FIFO with a packet of the maximum packet size. The packet is then ready to be sent to the host. When the last packet has been loaded by the DMA controller, the controller interrupts the processor. If the last packet loaded is less than the maximum packet size, the TXRDY bit is not set and therefore needs to be set manually (that is, by the CPU) to allow the last packet to be sent. The TXRDY bit also needs to be set manually if the last packet is of the maximum packet size and a null packet is to be sent to indicate the end of the transfer.
NOTE
If, when operating in host mode, the USB fails to successfully transmit a packet three times, the ERROR bit in the USBTXCSRLn register becomes set and the DMA request line is disabled until this ERROR bit is cleared again. It should also be noted that the DMAMOD bit in the USBTXCSRHn register must not be cleared either before or in the same cycle as the corresponding DMAEN bit is cleared.