SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
VSYNC (LCDFP signal) toggles after all lines in a frame have been transmitted to the LCD and a programmable number of line clock cycles has elapsed both at the beginning and end of each frame. The LCD Raster Timing 1 (LCDRASTRTIM1) register, offset 0x030, fully defines the behavior of this signal.
VSYNC can be programmed to be synchronized with the rising or falling edge of LCDCP pixel clock. The PXLCLKCTL and PSYNCRF bits in the LCD Raster Timing 2 (LCDRASTRTIM2) register, offset 0x034, are used to configure the synchronization.