SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The function of the watchdog timer module is to prevent system hangs. The MSP432E4 microcontroller has two watchdog timer modules in case one watchdog clock source fails. One watchdog is run off the system clock, and the other is run off the precision internal oscillator (PIOSC). The watchdog timer can be configured to generate an interrupt or a nonmaskable interrupt to the microcontroller on its first time-out and to generate a system reset or POR on its second time-out.
After the first time-out event of the watchdog, the 32-bit watchdog counter is reloaded with the value of the Watchdog Timer Load (WDTLOAD) register and resumes counting down from that value. If the timer counts down to zero again before the first time-out interrupt is cleared, and watchdog reset generation has been enabled through the RESEN bit in the Watchdog Control (WDTCTL) register, the watchdog timer asserts its reset signal to the microcontroller. The reset generated can be a full POR or a system reset depending on the value programmed in WDOGn bit field of the RESBEHAVCTL register:
The watchdog timer POR sequence is:
See the device-specific data sheet for watchdog time-out internal reset deassertion timing.
The watchdog timer system reset sequence is:
For more information on the Watchdog Timer module, see Section 28.