SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Watchdog Control (WDTCTL)
WDT0, reset = 0x0000.0000
WDT1, reset = 0x8000.0000
This register is the watchdog control register. The watchdog timer can be configured to generate a reset signal (on second time-out) or an interrupt on time-out.
When the watchdog interrupt has been enabled by setting the INTEN bit, all subsequent writes to the INTEN bit are ignored. The only mechanisms that can re-enable writes to this bit are a hardware reset or a software reset initiated by setting the appropriate bit in the Watchdog Timer Software Reset (SRWD) register.
NOTE
Because the Watchdog Timer 1 module has an independent clocking domain, its registers must be written with a timing gap between accesses. Software must guarantee that this delay is inserted between back-to-back writes to WDT1 registers or between a write followed by a read to the registers. The timing for back-to-back reads from the WDT1 module has no restrictions. The WRC bit in the Watchdog Control (WDTCTL) register for WDT1 indicates that the required timing gap has elapsed. This bit is cleared on a write operation and set once the write completes, indicating to software that another write or read may be started safely. Software should poll WDTCTL for WRC =1 prior to accessing another register. Note that WDT0 does not have this restriction as it runs off the system clock and therefore does not have a WRC bit.
WDTCTL is shown in Figure 28-4 and described in Table 28-5.
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| WRC | RESERVED | ||||||
| R-0x1 | R-0x0 | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0x0 | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0x0 | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | INTTYPE | RESEN | INTEN | ||||
| R-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | ||||