SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Watchdog Masked Interrupt Status (WDTMIS)
This register is the masked interrupt status register. The value of this register is the logical AND of the raw interrupt bit and the Watchdog interrupt enable bit.
WDTMIS is shown in Figure 28-7 and described in Table 28-8.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0x0 | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0x0 | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | WDTMIS | ||||||
R-0x0 | R-0x0 | ||||||