SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Watchdog Raw Interrupt Status (WDTRIS)
This register is the raw interrupt status register. Watchdog interrupt events can be monitored via this register if the controller interrupt is masked.
WDTRIS is shown in Figure 28-6 and described in Table 28-7.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0x0 | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0x0 | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | WDTRIS | ||||||
R-0x0 | R-0x0 | ||||||