There are many ADC use-cases from an operating mode and clocking standpoint but the majority of them will fit into one of the items below:
- Triggers in RUN or SLEEP mode
- If ADC is triggered to
start a conversion (software or Event), and the device is in RUN0 or
RUN1 or SLEEP0 or SLEEP1 mode
(SYSOSC is already running at any frequency), then:
- Sample clock can
be ULPCLK, HFCLK, or SYSOSC in this mode
- The conversion runs without changing SYSOSC frequency
- 4-MHz, 16-MHz, 24-MHz, or 32-MHz SYSOSC frequencies are
allowed
- If ADC is triggered to start a conversion (software or Event), and the device is in RUN2 or SLEEP2 mode (SYSOSC is disabled, MCLK = LFCLK = 32 kHz), then:
- Sample clock can be ULPCLK or SYSOSC in this mode
- SYSCTL interprets the ADC CLK REQ as an asynchronous fast clock request, enabling SYSOSC at 32 MHz and forcing MCLK or ULPCLK to 32 MHz MHz
until the ADC de-asserts the request
- CCONRUN must be cleared in this use case
- CCONSTOP must be cleared in this use case
- Triggers in STOP mode
- Sample clock can be ULPCLK or SYSOSC in this mode
- If ADC is triggered to
start a conversion (Event), and the device is in STOP0 mode (SYSOSC
runs at any frequency, ULPCLK = 4 MHz), then:
- The conversion runs without changing SYSOSC frequency
- 4-MHz, 16-MHz, 24-MHz, or 32-MHz SYSOSC frequencies are
allowed
- If ADC is triggered to start a conversion (Event), and the device is in STOP1 mode (SYSOSC was gear shifted to 4 MHz), then:
- SYSCTL forces SYSOSC to BASE (consistent with RUN mode because USE4MHZSTOP was set) when receiving ADC CLK REQ, and SYSCTL releases SYSOSC back to 4 MHz after the ADC CLK
REQ is removed
- CCONRUN must be cleared
- CCONSTOP must be cleared
- If ADC is triggered to start a conversion (Event), and the device is in STOP2 mode (SYSOSC disabled), then:
- The trigger event propagates through the event fabric at 32 kHz, the ADC receives the trigger and assert the ADC CLK REQ (CPCLK REQ) to SYSCTL, and SYSCTL receives the ADC
CLK REQ as an asynchronous fast clock request, suspending STOP, enabling SYSOSC at 32 MHz , and
forcing MCLK or ULPCLK to 32 MHz until the ADC de-asserts the ADC CLK REQ
- CCONRUN must be cleared
- CCONSTOP must be cleared
- Triggers in STANDBY mode
- Sample clock can be ULPCLK or SYSOSC in this mode
- If ADC is triggered to start a conversion (Event), and the device is in STANDBY0 mode (SYSOSC is disabled but ULPCLK is running), then:
- The trigger event propagates through event fabric at 32 kHz, the ADC receives the trigger and asserts the ADC CLK REQ (CPCLK REQ) to SYSCTL, and SYSCTL interprets the ADC
CLK REQ as an asynchronous fast clock request, suspending STANDBY, enabling SYSOSC at 32 MHz , and
forcing MCLK/ULPCLK to 32 MHz until the ADC de-asserts the ADC CLK REQ
- CCONRUN must be cleared
- CCONSTOP must be cleared
- If ADC is triggered to
start a conversion (Event-TIMG0
or TIMG1), and
the device is in STANDBY1 (ULPCLK is gated with STOPCLKSTBY set), then:
- The TIMG0 or
TIMG1 event triggers an asynchronous fast clock request to
suspend STANDBY mode, start SYSOSC at 32 MHz , and force MCLK or ULPCLK to 32 MHz z; there are then 32
SYSOSC cycles for the TIMG0 or TIMG1 event to proceed through
the event fabric and for the ADC to capture the timer event and
assert the ADC CLK REQ to hold the SYSOSC enabled to run the
conversion
- When the ADC
de-asserts the ADC CLK REQ, ULPCLK runs for 32
additional cycles to allow any ADC event (DMA request or IRQ) to
propagate, after which SYSCTL resumes STANDBY with STOPCLKSTBY
(STANDBY1)
- CCONRUN must be
cleared
- CCONSTOP must be
cleared