米6体育平台手机版

SLAU846A June 2023 – October 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1

1
Read This First
1. About This Manual
2. Notational Conventions
3. Glossary
4. Support Resources
5. Trademarks
1 Architecture
1. 1.1 Architecture Overview
2. 1.2 Bus Organization
3. 1.3 Platform Memory Map
4. 1.4 Boot Configuration
5. 1.5 NONMAIN Registers
6. 1.6 Factory Constants
  1. 1.6.1 FACTORYREGION Registers
2 PMCU
1. 2.1 PMCU Overview
  1. 2.1.1 Power Domains
  2. 2.1.2 Operating Modes
2. 2.2 Power Management (PMU)
3. 2.3 Clock Module (CKM)
4. 2.4 System Controller (SYSCTL)
5. 2.5 Quick Start Reference
6. 2.6 SYSCTL Registers
3 CPU
1. 3.1 Overview
2. 3.2 Arm Cortex-M0+ CPU
3. 3.3 Interrupts and Exceptions
4. 3.4 CPU Peripherals
5. 3.5 Read-Only Memory (ROM)
6. 3.6 CPUSS Registers
7. 3.7 WUC Registers
4 DMA
1. 4.1 DMA Overview
2. 4.2 DMA Operation
3. 4.3 DMA Registers
5 MATHACL
1. 5.1 Overview
2. 5.2 Data Format
3. 5.3 Basic Operation
4. 5.4 Configuration Details with Examples
5. 5.5 MATHACL Registers
6 NVM (Flash)
1. 6.1 NVM Overview
2. 6.2 Flash Memory Bank Organization
3. 6.3 Flash Controller
4. 6.4 Write Protection
5. 6.5 Read Interface
  1. 6.5.1 Bank Address Swapping
  2. 6.5.2 ECC Error Handling
    1. 6.5.2.1 Single bit (correctable) errors
    2. 6.5.2.2 Dual bit (uncorrectable) errors
6. 6.6 FLASHCTL Registers
7 Events
1. 7.1 Events Overview
2. 7.2 Events Operation
8 IOMUX
1. 8.1 IOMUX Overview
  1. 8.1.1 IO Types and Analog Sharing
2. 8.2 IOMUX Operation
3. 8.3 IOMUX (PINCMx) Register Format
4. 8.4 IOMUX Registers
9 GPIO
1. 9.1 GPIO Overview
2. 9.2 GPIO Operation
3. 9.3 GPIO Registers
10ADC
1. 10.1 ADC Overview
2. 10.2 ADC Operation
3. 10.3 ADC12 Registers
11COMP
1. 11.1 Comparator Overview
2. 11.2 Comparator Operation
3. 11.3 COMP Registers
12OPA
1. 12.1 OPA Overview
2. 12.2 OPA Operation
3. 12.3 OA Registers
13GPAMP
1. 13.1 GPAMP Overview
2. 13.2 GPAMP Operation
3. 13.3 GPAMP Registers
14DAC
1. 14.1 DAC Introduction
2. 14.2 DAC Operation
3. 14.3 DAC12 Registers
15VREF
1. 15.1 VREF Overview
2. 15.2 VREF Operation
3. 15.3 VREF Registers
16UART
1. 16.1 UART Overview
2. 16.2 UART Operation
3. 16.3 UART Registers
17SPI
1. 17.1 SPI Overview
2. 17.2 SPI Operation
3. 17.3 SPI Registers
18I2C
1. 18.1 I2C Overview
2. 18.2 I2C Operation
19I2C Registers
20CAN-FD
1. 20.1 MCAN Overview
  1. 20.1.1 MCAN Features
2. 20.2 MCAN Environment
3. 20.3 CAN Network Basics
4. 20.4 MCAN Functional Description
5. 20.5 MCAN Integration
6. 20.6 Interrupt and Event Support
  1. 20.6.1 CPU Interrupt Event Publisher (CPU_INT)
7. 20.7 MCAN Registers
21MCAN Registers
22CRC
1. 22.1 CRC Overview
  1. 22.1.1 CRC16-CCITT
  2. 22.1.2 CRC32-ISO3309
2. 22.2 CRC Operation
  1. 22.2.1 CRC Generator Implementation
  2. 22.2.2 Configuration
3. 22.3 CRC Registers
23AES
1. 23.1 AES Overview
  1. 23.1.1 AES Performance
2. 23.2 AES Operation
3. 23.3 AES Registers
24TRNG
1. 24.1 TRNG Overview
2. 24.2 TRNG Operation
3. 24.3 TRNG Registers
25Timers (TIMx)
1. 25.1 TIMx Overview
2. 25.2 TIMx Operation
3. 25.3 Timers (TIMx) Registers
26RTC
1. 26.1 Overview
2. 26.2 Basic Operation
3. 26.3 Configuration
4. 26.4 RTC Registers
27WWDT
1. 27.1 WWDT Overview
  1. 27.1.1 Watchdog Mode
  2. 27.1.2 Interval Timer Mode
2. 27.2 WWDT Operation
3. 27.3 WWDT Registers
28Debug
1. 28.1 Overview
2. 28.2 Debug Features
3. 28.3 Behavior in Low Power Modes
4. 28.4 Restricting Debug Access
5. 28.5 Mailbox (DSSM)
  1. 28.5.1 DSSM Events
    1. 28.5.1.1 CPU Interrupt Event (CPU_INT)
  2. 28.5.2 DEBUGSS Registers
29Revision History

11.2.1 Comparator Configuration

The comparator compares the analog voltages at the positive (+) and negative (–) input terminals. If the + terminal is more positive than the – terminal, the comparator output is high. The polarity of the comparator output can be configured by using the OUTPOL bit in COMPx.CTL1 register. The comparator can be switched on or off using ENABLE bit in COMPx.CTL1 register. The comparator should be switched off when not in use to reduce current consumption. When the comparator is off, OUT is low when OUTPOL bit is set to 0, and OUT is high when OUTPOL bit is set to 1.

The comparator can be configured in fast or ultra-low-power mode using MODE bit in COMPx.CTL1 register. The default value of MODE bit is 0 which configures the comparator in fast mode. When MODE bit is set to 1 the comparator is configured in ultra-low-power mode. In the fast mode the comparator consumes higher current but the response time is faster. In the ultra-low power mode the comparator consumes very low current but response time is slower. To optimize current consumption for the application, the power mode that meets the comparator speed requirements should be selected (please see the device-specific data sheet for the comparator propagation delay).

The clock control for comparator is managed by System Controller (SYSCTL), SYSCTL knows if comparator module is enabled and it also knows if it is in ultra-low-power mode or fast mode. User needs to ensure the proper bus clock is selected for different comparator operation mode:

For ultra-low-power mode comparator, bus clock can be LFCLK or any of the high speed clocks.
For fast mode comparator, bus clock cannot be LFCLK, system will generate a clock error interrupt in SYSCTL if you enable a comparator in fast mode and the bus clock is LFCLK.