米6体育平台手机版

SLAU847D October 2022 – May 2024 MSPM0L1105 , MSPM0L1106 , MSPM0L1227 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346 , MSPM0L2227 , MSPM0L2228 , MSPM0L2228-Q1

1
Read This First
1. About This Manual
2. Notational Conventions
3. Glossary
4. Related Documentation
5. Support Resources
6. Trademarks
1 Architecture
1. 1.1 Architecture Overview
2. 1.2 Bus Organization
3. 1.3 Platform Memory Map
4. 1.4 Boot Configuration
5. 1.5 NONMAIN_L1105_L1106_L1303_L1304_L1305_L1306_L1343_L1344_L1345_L1346 Registers
6. 1.6 NONMAIN_L1227_L1228_L2227_L2228 Registers
7. 1.7 Factory Constants
  1. 1.7.1 FACTORYREGION Registers
2 PMCU
1. 2.1 PMCU Overview
  1. 2.1.1 Power Domains
  2. 2.1.2 Operating Modes
2. 2.2 Power Management (PMU)
3. 2.3 Clock Module (CKM)
4. 2.4 System Controller (SYSCTL)
5. 2.5 Quick Start Reference
6. 2.6 SYSCTL_L1105_L1106_L1303_L1304_L1305_L1306_L1343_L1344_L1345_L1346 Registers
7. 2.7 SYSCTL_L1227_L1228_L2227_L2228 Registers
3 CPU
1. 3.1 Overview
2. 3.2 Arm Cortex-M0+ CPU
3. 3.3 Interrupts and Exceptions
4. 3.4 CPU Peripherals
  1. 3.4.1 System Control Block (SCB)
  2. 3.4.2 System Tick Timer (SysTick)
5. 3.5 Read-Only Memory (ROM)
6. 3.6 CPUSS Registers
7. 3.7 WUC Registers
4 SECURITY
1. 4.1 Overview
  1. 4.1.1 Secure Boot
  2. 4.1.2 Customer Secure Code (CSC)
2. 4.2 Boot and Startup Sequence
  1. 4.2.1 CSC Programming Overview
3. 4.3 Secure Key Storage
4. 4.4 Flash Memory Protection
5. 4.5 SRAM Protection
6. 4.6 SECURITY Registers
5 DMA
1. 5.1 DMA Overview
2. 5.2 DMA Operation
3. 5.3 DMA Registers
6 NVM (Flash)
1. 6.1 NVM Overview
2. 6.2 Flash Memory Bank Organization
3. 6.3 Flash Controller
4. 6.4 Write Protection
5. 6.5 Read Interface
  1. 6.5.1 Bank Address Swapping
6. 6.6 FLASHCTL Registers
7 Events
1. 7.1 Events Overview
2. 7.2 Events Operation
8 Low Frequency Subsystem (LFSS)
1. 8.1 Overview
2. 8.2 Clock System
3. 8.3 LFSS Reset Using VBAT
4. 8.4 Power Domains and Supply Detection
5. 8.5 Real Time Counter (RTC_x)
6. 8.6 Independent Watchdog Timer (IWDT)
7. 8.7 Tamper Input and Output
  1. 8.7.1 IOMUX Mode
  2. 8.7.2 Tamper Mode
8. 8.8 Scratchpad Memory
9. 8.9 Lock Function of RTC, TIO, and WDT
10. 8.10 LFSS Registers
9 IOMUX
1. 9.1 IOMUX Overview
  1. 9.1.1 IO Types and Analog Sharing
2. 9.2 IOMUX Operation
3. 9.3 IOMUX (PINCMx) Register Format
4. 9.4 IOMUX Registers
10TRNG
1. 10.1 TRNG Overview
2. 10.2 TRNG Operation
3. 10.3 TRNG Registers
11AESADV
1. 11.1 AESADV Overview
  1. 11.1.1 AESADV Performance
2. 11.2 AESADV Operation
3. 11.3 AESADV Registers
12Keystore
1. 12.1 Overview
2. 12.2 Detailed Description
3. 12.3 KEYSTORECTL Registers
13GPIO
1. 13.1 GPIO Overview
2. 13.2 GPIO Operation
3. 13.3 GPIO Registers
14ADC
1. 14.1 ADC Overview
2. 14.2 ADC Operation
3. 14.3 ADC12 Registers
15COMP
1. 15.1 Comparator Overview
2. 15.2 Comparator Operation
3. 15.3 COMP Registers
16OPA
1. 16.1 OPA Overview
2. 16.2 OPA Operation
3. 16.3 OA Registers
17GPAMP
1. 17.1 GPAMP Overview
2. 17.2 GPAMP Operation
3. 17.3 GPAMP Registers
18VREF
1. 18.1 VREF Overview
2. 18.2 VREF Operation
3. 18.3 VREF Registers
19UART
1. 19.1 UART Overview
2. 19.2 UART Operation
3. 19.3 UART Registers
20SPI
1. 20.1 SPI Overview
2. 20.2 SPI Operation
3. 20.3 SPI Registers
21I2C
1. 21.1 I2C Overview
2. 21.2 I2C Operation
3. 21.3 I2C Registers
22CRC
1. 22.1 CRC Overview
  1. 22.1.1 CRC16-CCITT
  2. 22.1.2 CRC32-ISO3309
2. 22.2 CRC Operation
  1. 22.2.1 CRC Generator Implementation
  2. 22.2.2 Configuration
3. 22.3 CRC Registers
23Timers (TIMx)
1. 23.1 TIMx Overview
2. 23.2 TIMx Operation
3. 23.3 TIMx Registers
24LCD
1. 24.1 LCD Introduction
2. 24.2 LCD Clocking
3. 24.3 Voltage Generation
4. 24.4 Analog Mux
5. 24.5 LCD Memory and output drive
  1. 24.5.1 LCD Memory organization
6. 24.6 IO Muxing
7. 24.7 Interrupt Generation
8. 24.8 Power Domains and Power Modes
9. 24.9 LCD Registers
25RTC
1. 25.1 Overview
  1. 25.1.1 RTC Instances
2. 25.2 Basic Operation
3. 25.3 Configuration
4. 25.4 RTC Registers
26IWDT
1. 26.1 IWDT Initialization after LFSS Reset
2. 26.2 IWDT Clock Configuration
3. 26.3 IWDT Period Selection
4. 26.4 Debug Behavior of the IWDT
5. 26.5 IWDT Registers
27WWDT
1. 27.1 WWDT Overview
  1. 27.1.1 Watchdog Mode
  2. 27.1.2 Interval Timer Mode
2. 27.2 WWDT Operation
3. 27.3 WWDT Registers
28Debug
1. 28.1 Overview
2. 28.2 Debug Features
3. 28.3 Behavior in Low Power Modes
4. 28.4 Restricting Debug Access
5. 28.5 Mailbox (DSSM)
  1. 28.5.1 DSSM Events
    1. 28.5.1.1 CPU Interrupt Event (CPU_INT)
  2. 28.5.2 DEBUGSS Registers
29Revision History

19.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)

DMA_TRIG_RX and DMA_TRIG_TX registers are used to setup the trigger signaling for the DMA. This can be setup in a flexible way to trigger the DMA for receive or transmit events with the trigger conditions in Table 21-76and Table 19-10.

DMA_TRIG_RX is used for triggering the DMA to do a receive data transfer and DMA_TRIG_TX is used for triggering the DMA to do a transmit data transfer.

Table 19-9 UART DMA Trigger Condition (DMA_TRIG_RX)

IIDX STAT	Name	Description
0x01	RTOUT	UART receive timeout interrupt, This interrupt is asserted when the receive FIFO is not empty, and no further data is received specified time in the UARTx.IFLS.RXTOSEL bits. More information provided below.
0x0B	RXINT	UART receive interrupt. More information provided below.

The receive timeout interrupt is asserted when the receive FIFO is not empty, and no further data is received specified time in the IFLS.RXTOSEL bits. The receive timeout interrupt is cleared either when the FIFO becomes empty through reading all the data (or by reading the holding register), by reading the interrupt index from IIDX or when a 1 is written to the corresponding bit in the ICLR register.

The receive interrupt (RXINT, 0x0B) changes state when one of the following events occurs:

If the FIFOs are enabled and the receive FIFO reaches the programmed trigger level, the RXINT bit is set. The receive interrupt is cleared by reading data from the receive FIFO until it becomes less than the trigger level, by reading the interrupt index from IIDX or by writing a 1 to the RXINT bit in ICLR.
If the FIFOs are disabled (have a depth of one location) and data is received thereby filling the location, the RXINT bit is set. The receive interrupt is cleared by performing a single read of the receive FIFO, by reading the interrupt index from IIDX or by writing a 1 to the RXINT bit in ICLR.

Table 19-10 UART DMA Trigger Condition (DMA_TRIG_TX)

IIDX STAT	Name	Description
0x0C	TXINT	UART transmit interrupt. More information provided below.

The transmit interrupt (TXINT, 0x0C) changes state when one of the following events occurs:

If the FIFOs are enabled and the transmit FIFO progresses through the programmed trigger level, the TXINT bit is set. The transmit interrupt is based on a transition through level, therefore the FIFO must be written past the programmed trigger level otherwise no further transmit interrupts will be generated. The transmit interrupt is cleared by writing data to the transmit FIFO until it becomes greater than the trigger level, by reading the interrupt index from IIDX or by writing a 1 to the TXINT bit in ICLR.
If the FIFOs are disabled (have a depth of one location) and there is no data present in the transmitters single location, the TXINT bit is set. It is cleared by performing a single write to the transmit FIFO, by reading the interrupt index from IIDX or by writing a 1 to the TXINT bit in ICLR.

The DMA trigger event configuration is managed with the DMA_TRIG_RX and DMA_TRIG_TX event management registers. See Section 7.2.5 for guidance on configuring the Event registers and Section 7.1.3.2 for on how DMA trigger event works.