SLAU860A June   2021  – November 2021 TAS5828M

 

  1. 1Trademarks
  2. 2Hardware Overview
    1. 2.1 Features
    2. 2.2 Functions
    3. 2.3 Detailed Operations
  3. 3Hardware Setup
    1. 3.1 I2C Device Addresses
  4. 4Schematics
  5. 5Board Layouts
  6. 6Bill of Materials
  7. 7Revision History

Detailed Operations

The TAS5828MEVM only requires a single supply to operate. Three different audio sources can be selected:

  1. If XMOS is selected manually by toggling the S2 switch, the Windows Media Player can be used to stream audio.
  2. If SPDIF is selected manually by toggling the S2 switch, a DVD player with an optical cable or an analog cable can be used to provide audio stream.
  3. If external digital audio source such as Programmable Serial Interface Adapter (PSIA) from Audio Precision, jumpers can be used to insert external I2S signals.

Both 3.3 V and 1.8 V DVDD and IOVDD are supported with TAS5828MEVM. Jumper (J26) can be used to select accordingly based on requirement.

TAS5828MEVM provides optional onboard LM5155 boost Hybrid-Pro evaluation or external customer system boost with Hybrid-Pro feedback (HPFB pin) control:

  1. Onboard LM5155 boost Hybrid-Pro evaluation
    • 5 V battery power input through J12 and J13. Bypass external PVDD through DNP J18
    • TAS5828M PVDD is from LM5155 boost output: J14 - IN, J18 - OUT
    • TAS5828M HPFB pin routes to LM5155 FB pin: J15 - IN, J16 - OUT
  2. External customer system boost with Hybrid-Pro feedback (HPFB pin) control
    • TAS5828M HPFB pin routes for external customer system boost FB control through TP7 FB and TP8 GND: J15 - OUT, J16 - OUT
    • Customer system boost output for TAS5828M PVDD through J17 PVDD and J20 GND: J14 - OUT, J18 - IN

The USB connection is also used to provide I2C communications with the two TAS5828M devices on the EVM. The Pure Path Console 3 (PPC3) is the software tool which can initialize and operate this EVM.

Alternatively, the TAS5828M has an optional Hardware Control Mode to set switching frequency, analog gain, BTL/PBTL mode and Cycle by Cycle current limit through pin configuration. Hardware Control Mode can be enable by modifying J8 ADR/HW to HW, J10 SDA/HW_SEL0 to desired mode according to Table 2-2, and J11 SCK/HW_SEL1 to the desired mode according to Table 2-1.

Table 2-1 Hardware Control - HW_SEL1 Pin6
R10(GND) R8(DVDD) FSW&Class D Loop Bandwidth Cycle By Cycle Current Limit Threshold Spread Spectrum Modulation
0 Ω DNP 768 kHz FSW, 175 kHz BW CBC Threshold = 80% OCP Disable 1SPW
1 kΩ DNP 768 kHz FSW, 175 kHz BW CBC Disable Disable 1SPW
4.7 kΩ DNP 768 kHz FSW, 175 kHz BW CBC Threshold = 40% OCP Disable 1SPW
15 kΩ DNP 768 kHz FSW, 175 kHz BW CBC Threshold = 60% OCP Disable 1SPW
DNP 33 kΩ 480 kHz FSW, 100 kHz BW CBC Disable Enable BD
DNP 6.8 kΩ 480 kHz FSW, 100 kHz BW CBC Threshold = 80% OCP Enable BD
DNP 1.5 kΩ 480 kHz FSW, 100 kHz BW CBC Threshold = 40% OCP Enable BD
DNP 0 Ω 480 kHz FSW, 100 kHz BW CBC Threshold = 60% OCP Enable BD
Table 2-2 Hardware Control - HW_SEL0 Pin5
R11(GND) R9(DVDD) Analog Gain H-Bridge Output Configuration
0 Ω DNP 29.5 VP/FS BTL
1 kΩ DNP 20.9 VP/FS BTL
4.7 kΩ DNP 14.7 VP/FS BTL
15 kΩ DNP 7.4 VP/FS BTL
DNP 33 kΩ 7.4 VP/FS PBTL
DNP 6.8 kΩ 14.7 VP/FS PBTL
DNP 1.5 kΩ 20.9 VP/FS PBTL
DNP 0 Ω 29.5 VP/FS PBTL