All the required clocking is generated on the EVM and no external clock signal is required. The LMK61E2 generates the reference frequency LMK00304 make two copies of the reference signal and sends the one copy to LMX2594 to generate the sampling clock for the ADC and LMK04828 uses the second copy in clock distribution mode to provides the FPGA reference clock, FPGA SYSREF signal and ADC SYSREF signal.
Figure 6-2 shows the block diagram of onboard clocking option:

The EVM can be configured to use onboard clocking option with the following steps (see Figure 6-5):

• Remove C2 and C3, populate R171 and R174
• Remove C60 and C61, populate C52 and C306
• Uninstall Jumper J13

Figure 6-2 Onboard Clocking System Block Diagram