By default, the EVM is configured to use the external clock option. The user provide and external clock signal for both the ADC sampling clock (DEVCLK at J10) and also the reference clock (REF CLK at J17) which feed into the LMK04828 and is used in clock distribution mode and provides the FPGA reference clock, FPGA SYSREF signal and ADC SYSREF signal. If coherent sampling is desired the external clocking has to be used. Figure 6-1 shows the block diagram of external clocking option:

The EVM can be configured to use external clocks with the following steps (see Figure 6-4):

1. Modify the hardware:
   1. Remove R171 and R174, populate C2 and C3.
   2. Remove C52 and C306, populate C60 and C61
   3. Install Jumper J13

Figure 6-1 ADCxxDJxx00RF-TRF1208-EVM Clocking System Block Diagram