4 System Overview

ULC1001 has many settings to be configured for good cleaning performance. These settings are separated into three main tabs: Calibration, Cleaning Modes, and Power and Diagnostics. At a high level, ULC1001 invokes modes for calibration, cleaning, power monitoring, and fault protection. Each of these nine modes contains up to 30 bursts that can be configured for a wide range of frequencies. Bursts are enumerated from 0-23 and each burst has eight configurable parameters. The GUI is very useful for setting up the system and exporting configuration files for system integration. When a mode is enabled, the ULC1001-DRV290x EVM drives each burst in the order shown in Figure 4-1 for a given mode.

There are two types of bursts: Active bursts enable the IV sense path (bursts 0 to 5 and 19 to 23) and Passive bursts do not enable the IV sense path (bursts 6 to 17). Each burst contains the following eight configurable parameters: Amp, Delay, and Duration, Freq_Start, Freq_Stop, Num_Freq, Delta_Freq, and Modulation.

All Active burst frequency settings, except burst 0, must follow the following: Delta_Freq*n = (Fs/N)*n = (ULC_RX_mode_cfg bits [0-4]/USER_Params_numSamples)*n, where n is an integer multiplier. Freq_start ≤ Freq_stop. Freq_start and Freq_stop must be integer multiples of Delta_Freq. Refer to Table 5-2.

All Passive bursts must have Num_Freq = 0. Refer to Table 5-3.

There are two types of registers to be programmed. Hardware (HW) registers, which are 8-bits, setup the hardware configurations such as the ADC sample rate. Firmware (FW) registers, which are 32-bits and follow a Q-point notation, setup the firmware inside the DSP. FW registers' Q-point notation is defined by the suffix of each register; if no suffix exists, then the register is a normal 32-bit register. FW registers are stored in an I2C buffer and are not used by the firmware until the re-initialization command is invoked. Refer to Section 5.5.3 for running the re-initialization command.