SLAZ094AB October   2012  – May 2021 CC430F5137

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      RGZ48
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  ADC24
    2. 6.2  ADC25
    3. 6.3  ADC27
    4. 6.4  ADC29
    5. 6.5  ADC42
    6. 6.6  ADC69
    7. 6.7  AES1
    8. 6.8  BSL7
    9. 6.9  COMP4
    10. 6.10 COMP10
    11. 6.11 CPU18
    12. 6.12 CPU20
    13. 6.13 CPU21
    14. 6.14 CPU22
    15. 6.15 CPU23
    16. 6.16 CPU24
    17. 6.17 CPU25
    18. 6.18 CPU26
    19. 6.19 CPU27
    20. 6.20 CPU28
    21. 6.21 CPU29
    22. 6.22 CPU30
    23. 6.23 CPU31
    24. 6.24 CPU32
    25. 6.25 CPU33
    26. 6.26 CPU34
    27. 6.27 CPU35
    28. 6.28 CPU39
    29. 6.29 CPU40
    30. 6.30 CPU46
    31. 6.31 CPU47
    32. 6.32 DMA4
    33. 6.33 DMA7
    34. 6.34 DMA8
    35. 6.35 DMA10
    36. 6.36 EEM8
    37. 6.37 EEM9
    38. 6.38 EEM11
    39. 6.39 EEM13
    40. 6.40 EEM14
    41. 6.41 EEM16
    42. 6.42 EEM17
    43. 6.43 EEM19
    44. 6.44 EEM23
    45. 6.45 FLASH29
    46. 6.46 FLASH31
    47. 6.47 FLASH37
    48. 6.48 JTAG20
    49. 6.49 JTAG26
    50. 6.50 JTAG27
    51. 6.51 MPY1
    52. 6.52 PMAP1
    53. 6.53 PMM8
    54. 6.54 PMM9
    55. 6.55 PMM10
    56. 6.56 PMM11
    57. 6.57 PMM12
    58. 6.58 PMM14
    59. 6.59 PMM15
    60. 6.60 PMM17
    61. 6.61 PMM18
    62. 6.62 PMM20
    63. 6.63 PORT15
    64. 6.64 PORT16
    65. 6.65 PORT17
    66. 6.66 PORT19
    67. 6.67 PORT21
    68. 6.68 RF1A1
    69. 6.69 RF1A2
    70. 6.70 RF1A3
    71. 6.71 RF1A5
    72. 6.72 RF1A6
    73. 6.73 RF1A8
    74. 6.74 RTC3
    75. 6.75 RTC6
    76. 6.76 SYS16
    77. 6.77 TAB23
    78. 6.78 UCS6
    79. 6.79 UCS7
    80. 6.80 UCS9
    81. 6.81 UCS10
    82. 6.82 UCS11
    83. 6.83 USCI26
    84. 6.84 USCI30
    85. 6.85 USCI31
    86. 6.86 USCI34
    87. 6.87 USCI35
    88. 6.88 USCI39
    89. 6.89 USCI40
    90. 6.90 WDG4
  7. 7Revision History

PMM15

PMM Module

Category

Functional

Function

Device may not wake up from LPM2, LPM3, or LPM4

Description

Device may not wake up from LPM2, LPM3 or LMP4 if an interrupt occurs within 1 us after the entry to the specified LPMx; entry can be caused either by user code or automatically (for example, after a previous ISR is completed). Device can be recovered with an external reset or a power cycle. Additionally, a PUC can also be used to reset the failing condition and bring the device back to normal operation (for example, a PUC caused by the WDT).

This effect is seen when:
- A write to the SVSMHCTL and SVSMLCTL registers is immediately followed by an LPM2, LPM3, LPM4 entry without waiting the requisite settling time ((PMMIFG.SVSMLDLYIFG = 0 and PMMIFG.SVSMHDLYIFG = 0)).

or

The following two conditions are met:

- The SVSL module is configured for a fast wake-up or when the SVSL/SVML module is turned off. The affected SVSMLCTL register settings are shaded in the following table.


GUID-20201119-CA0I-RD0T-58PG-VHRCJ71FXJT6-low.png


and

-The SVSH/SVMH module is configured to transition from Normal mode to an OFF state when moving from Active/LPM0/LPM1 into LPM2/LPM3/LPM4 modes. The affected SVSMHCTL register settings are shaded in the following table.


GUID-20201119-CA0I-HRBM-DP5W-NFBNZBTTJFBM-low.png

Workaround

Any write to the SVSMxCTL register must be followed by a settling delay (PMMIFG.SVSMLDLYIFG = 0 and PMMIFG.SVSMHDLYIFG = 0) before entering LPM2, LPM3, LPM4.

and

1. Ensure the SVSx, SVMx are configured to prevent the issue from occurring by the following:

- Configure the SVSL module for slow wake up (SVSLFP = 0). Note that this will increase the wakeup time from LPM2/3/4 to twakeupslow (~150 us).

or

- Do not configure the SVSH/SVMH such that the modules transition from Normal mode to an OFF state on LPM entry and ensure SVSH/SVMH is in manual mode. Instead force the modules to remain ON even in LPMx. Note that this will cause increased power consumption when in LPMx.

Refer to the MSP430 Driver Library(MSPDRIVERLIB) for proper PMM configuration functions.
Use the following function, PMM15Check (void), to determine whether or not the existing PMM configuration is affected by the erratum. The return value of the function is 1 if the configuration is affected, and 0 if the configuration is not affected.

unsigned char PMM15Check (void)
{
   // First check if SVSL/SVML is configured for fast wake-up
   if ( (!(SVSMLCTL & SVSLE)) || ((SVSMLCTL & SVSLE) && (SVSMLCTL & SVSLFP)) ||
        (!(SVSMLCTL & SVMLE)) || ((SVSMLCTL & SVMLE) && (SVSMLCTL & SVMLFP)) )
   { // Next Check SVSH/SVMH settings to see if settings are affected by PMM15
      if ((SVSMHCTL & SVSHE) && (!(SVSMHCTL & SVSHFP)))
      {
         if ( (!(SVSMHCTL & SVSHMD)) || ((SVSMHCTL & SVSHMD) &&
              (SVSMHCTL & SVSMHACE)) )
           return 1; // SVSH affected configurations
      }
      if ((SVSMHCTL & SVMHE) && (!(SVSMHCTL & SVMHFP)) && (SVSMHCTL & SVSMHACE))
          return 1; // SVMH affected configurations
      }
      return 0; // SVS/M settings not affected by PMM15
   }
}

2. If fast servicing of interrupts is required, add a 150us delay either in the interrupt service routine or before entry into LPM3/LPM4.